Abstract: A symbol decoding system incorporated in a plurality of NMOS/LSI chips generates data representing numerical characters encoded in the symbol. Scanning means generates signals in response to the scanning of a plurality of bars and spaces, which signals are decoded by a first chip as valid and invalid characters, the valid characters being recognized by a second chip which stores the valid characters and enables a microprocessor chip to receive the valid characters assembled as part of the symbol for processing thereof. Logic circuits enable test numerical characters to be generated in response to test signals outputted by the microprocessor chip.