Patents by Inventor Syed Neyaz IMAM

Syed Neyaz IMAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method for forming the same
    Patent number: 11201209
    Abstract: A method includes providing a semiconductor substrate, and forming a first N-type implant region and a second N-type implant region in the semiconductor substrate. The first N-type implant region and the second N-type implant region are separated by a portion of the semiconductor substrate. The method also includes forming a first P-type implant region in the semiconductor substrate, and performing a heat treatment process on the semiconductor substrate to form an N-type well region and a P-type well region in the semiconductor substrate. The N-type well region has a first portion, a second portion, and a third portion between the first portion and the second portion. The doping concentration of the third portion is lower than the doping concentration of the first portion and the doping concentration of the second portion.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 14, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Syed Neyaz Imam, Po-An Chen
  • High-voltage semiconductor devices and methods for manufacturing the same
    Patent number: 11081580
    Abstract: A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, and a first high-voltage well region disposed in the semiconductor substrate and having a second conductivity type that is opposite to the first conductivity type. The high-voltage semiconductor device also includes a first buried layer disposed on the first high-voltage well region and having the first conductivity type, and a second buried layer and a third buried layer disposed on the first high-voltage well region and having the second conductivity type, wherein the first buried layer is between the second buried layer and the third buried layer. The high-voltage semiconductor device further includes a source region and a drain region disposed on the first buried layer and having the second conductivity type.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 3, 2021
    Assignee: Nuvoton Technology Corporation
    Inventors: Gene Sheu, Vivek Ningaraju, Po-An Chen, Shaik Mastanbasheer, Pooja Ravindra Deshmane, Monika Bharti, Syed Neyaz Imam
  • SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20200203475
    Abstract: A method includes providing a semiconductor substrate, and forming a first N-type implant region and a second N-type implant region in the semiconductor substrate. The first N-type implant region and the second N-type implant region are separated by a portion of the semiconductor substrate. The method also includes forming a first P-type implant region in the semiconductor substrate, and performing a heat treatment process on the semiconductor substrate to form an N-type well region and a P-type well region in the semiconductor substrate. The N-type well region has a first portion, a second portion, and a third portion between the first portion and the second portion. The doping concentration of the third portion is lower than the doping concentration of the first portion and the doping concentration of the second portion.
    Type: Application
    Filed: November 22, 2019
    Publication date: June 25, 2020
    Inventors: Syed Neyaz Imam, Po-An Chen
  • HIGH -VOLTAGE SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME
    Publication number: 20200044080
    Abstract: A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, and a first high-voltage well region disposed in the semiconductor substrate and having a second conductivity type that is opposite to the first conductivity type. The high-voltage semiconductor device also includes a first buried layer disposed on the first high-voltage well region and having the first conductivity type, and a second buried layer and a third buried layer disposed on the first high-voltage well region and having the second conductivity type, wherein the first buried layer is between the second buried layer and the third buried layer. The high-voltage semiconductor device further includes a source region and a drain region disposed on the first buried layer and having the second conductivity type.
    Type: Application
    Filed: December 14, 2018
    Publication date: February 6, 2020
    Inventors: Gene SHEU, Vivek NINGARAJU, Po-An CHEN, Shaik MASTANBASHEER, Pooja Ravindra DESHMANE, Monika BHARTI, Syed Neyaz IMAM