Patents by Inventor SYED SHAKIR IQBAL

SYED SHAKIR IQBAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12028067
    Abstract: The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element) to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 2, 2024
    Assignee: Google LLC
    Inventor: Syed Shakir Iqbal
  • Publication number: 20240171179
    Abstract: The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.
    Type: Application
    Filed: June 21, 2021
    Publication date: May 23, 2024
    Applicant: Google LLC
    Inventor: Syed Shakir Iqbal
  • Patent number: 9569570
    Abstract: A configurable delay cell for an integrated circuit includes a CMOS inverter and first through fourth transistors. A drain of the third transistor is connected to a drain of the fourth transistor for generating an output signal. A connection between an output terminal of the CMOS inverter and a source of the first transistor, a connection between the output terminal of the CMOS inverter and a drain of the second transistor, and a connection between the source of the first transistor and the drain of the second transistor are configurable, using an electronic design automation (EDA) tool, for achieving first, second, third, fourth, and fifth delay values. The resulting delay value can be programmed by making changes only in one or more of the metal layers of the integrated circuit.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: February 14, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Gourav Kapoor, Gaurav Gupta, Syed Shakir Iqbal
  • Patent number: 9473121
    Abstract: A scannable flip-flop circuit and method for low power scan operation are provided. The scannable flip-flop includes a flip-flop for receiving an input signal, and for generating a flip-flop output signal. The scannable flip-flop also includes a voltage selection circuit coupled to the flip-flop. The voltage selection circuit supplies a first voltage to the flip-flop during a first state of a voltage selection signal, and supplies a second voltage to the flip-flop during a second state of the voltage selection signal. A series of scannable flip-flops may be arranged in a scan chain for testing during a scan test mode.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 18, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Kumar Abhishek, Gaurav Goyal, Syed Shakir Iqbal
  • Publication number: 20160292333
    Abstract: A configurable delay cell for an integrated circuit includes a CMOS inverter and first through fourth transistors. A drain of the third transistor is connected to a drain of the fourth transistor for generating an output signal. A connection between an output terminal of the CMOS inverter and a source of the first transistor, a connection between the output terminal of the CMOS inverter and a drain of the second transistor, and a connection between the source of the first transistor and the drain of the second transistor are configurable, using an electronic design automation (EDA) tool, for achieving first, second, third, fourth, and fifth delay values. The resulting delay value can be programmed by making changes only in one or more of the metal layers of the integrated circuit.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: GOURAV KAPOOR, Gaurav Gupta, Syed Shakir Iqbal
  • Publication number: 20160234529
    Abstract: A method for encoding and decoding data includes obtaining sets of pixels from transformed data. A linear index address is obtained from an address of the pixels to obtain a memory transformed address. The memory transformed address is used to obtain a set size of the pixels. Based on the set size and a threshold value, the pixel type is identified from a list of pixel types. Based on the pixel type, a bit stream having a refinement bit is generated.
    Type: Application
    Filed: February 5, 2015
    Publication date: August 11, 2016
    Inventor: SYED SHAKIR IQBAL