Abstract: One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation system additionally comprises a configuration file that identifies a subset of the emulated registers. The simulation system is configured with the configuration file to selectively mirror, during the hybrid emulation, the subset of the emulated registers identified by the configuration file.

Abstract: A hybrid electronic system including an emulator side including a processor and a first clock, a simulated side including one or more models to simulate one or more prototypes and a second clock, a first interface to the emulator side, and a second interface to the simulated side is disclosed. The processor is configured to determine using the first interface a first amount of time corresponding to an amount of time advanced on the emulator side by the first clock. The processor is configured to determine using the second interface a second amount of time corresponding to an amount of time advanced on the simulated side by the second clock, and set a value of a clock frequency of the second clock based on an initial value of the clock frequency of the second clock and a ratio of the first amount of time to the second amount of time.

Abstract: A hybrid electronic system including an emulator side including a processor and a first clock, a simulated side including one or more models to simulate one or more prototypes and a second clock, a first interface to the emulator side, and a second interface to the simulated side is disclosed. The processor is configured to determine using the first interface a first amount of time corresponding to an amount of time advanced on the emulator side by the first clock. The processor is configured to determine using the second interface a second amount of time corresponding to an amount of time advanced on the simulated side by the second clock, and set a value of a clock frequency of the second clock based on an initial value of the clock frequency of the second clock and a ratio of the first amount of time to the second amount of time.