Abstract: An optoelectronic component includes an optical transducer made of III-V semiconductor material and an optical scanning microelectromechanical system comprising a mirror. The optical transducer and the optical scanning microelectromechanical system are produced on a common wafer comprising at least a first layer made of silicon or silicon nitride with a thickness of less than one micron and wherein at least the mirror and its holding springs are produced. In a first variant, the mobile parts of the optical scanning microelectromechanical system are produced in various layers of silicon. In a second variant, the mobile parts of the optical scanning microelectromechanical system are produced in the layer of III-V semiconductor material.

Abstract: A high-mobility field-effect transistor, includes a stack along a Z axis, deposited on a substrate and comprising a buffer layer, a barrier layer, a heterojunction between the buffer layer and the barrier layer, and a two-dimensional electron gas localized in an XY plane perpendicular to the axis Z and in the vicinity of the heterojunction, a source, a drain, and a gate deposited on an upper face of the barrier layer, between the source and the drain, a first dielectric layer having a relative permittivity ?r and a thickness e which are such that: 0.5 nm?e/?r?2 nm, a metal pad arranged between the gate and the drain and deposited on the first dielectric layer, the metal pad being electrically connected to the gate.

Abstract: A power switching cell, and associated multi-level converter, include an input port capable of receiving a switching control signal, an input transistor linked by the gate to the input port, and by the source to a reference voltage, a self-biasing circuit comprising a self-biasing transistor linked by the gate to the drain of the input transistor, and a resistor connected in parallel between the gate and the source of the self-biasing transistor, and in series between the drain of the input transistor and the source of the self-biasing transistor, a power transistor, linked by the gate to the source of the self-biasing transistor and by the drain to a power supply voltage, and an isolating transistor linked by the gate and by the source to the gate and to the source of the power transistor, and by the drain to the output port of the cell.

Abstract: A power switching cell, and associated multi-level converter, include an input port capable of receiving a switching control signal, an input transistor linked by the gate to the input port, and by the source to a reference voltage, a self-biasing circuit comprising a self-biasing transistor linked by the gate to the drain of the input transistor, and a resistor connected in parallel between the gate and the source of the self-biasing transistor, and in series between the drain of the input transistor and the source of the self-biasing transistor, a power transistor, linked by the gate to the source of the self-biasing transistor and by the drain to a power supply voltage, and an isolating transistor linked by the gate and by the source to the gate and to the source of the power transistor, and by the drain to the output port of the cell.

Abstract: A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.

Abstract: A field-effect transistor comprising a stack of semiconductor materials, the upper face of the stack being covered with a passivation layer comprises two sub-layers: a first sub-layer extending over a second zone of low intensity comprising a first material with electric breakdown field Ecl1, the charge of the first sub-layer being strictly less than the charge of the upper face of the stack, a second sub-layer extending over a first zone of high intensity and covering the first sub-layer, the second sub-layer comprising a second material with electrical breakdown field Ecl2 strictly greater than Ecl1.

Abstract: A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.

Abstract: A semiconductor device for electron emission in a vacuum comprises a stack of two or more semi-conductor layers of N and P type according to sequence N/(P)/N forming a juxtaposition of two head-to-tail NP junctions, in materials belonging to the III-N family, two adjacent layers forming an interface. The semiconductor materials of the layers of the stack close to the vacuum, where the electrons reach a high energy, have a band gap Eg>c/2, where c is the electron affinity of the semiconductor material, the P-type semiconductor layer being obtained partially or completely, by doping impurities of acceptor type or by piezoelectric effect to exhibit a negative fixed charge in any interface between the layers, a positive bias potential applied to the stack supplying, to a fraction of electrons circulating in the stack, the energy needed for emission in the vacuum by an emissive zone of an output layer.

Abstract: A semiconductor device for electron emission in a vacuum comprises a stack of two or more semi-conductor layers of N and P type according to sequence N/(P)/N forming a juxtaposition of two head-to-tail NP junctions, in materials belonging to the III-N family, two adjacent layers forming an interface. The semiconductor materials of the layers of the stack close to the vacuum, where the electrons reach a high energy, have a band gap Eg>c/2, where c is the electron affinity of the semiconductor material, the P-type semiconductor layer being obtained partially or completely, by doping impurities of acceptor type or by piezoelectric effect to exhibit a negative fixed charge in any interface between the layers, a positive bias potential applied to the stack supplying, to a fraction of electrons circulating in the stack, the energy needed for emission in the vacuum by an emissive zone of an output layer.

Abstract: A collector-up heterojunction bipolar transistor including, stacked on a substrate, an emitter layer, a base layer, and a collector layer. In this transistor the surface area of the base-emitter junction is of smaller dimensions than the surface area of the base-collector junction. Further, the material of the base layer exhibits a sensitivity of the electrical conductivity to ion implantation that is lower than the sensitivity of the electrical conductivity of the material of the emitter layer to the same ion implantation.

Abstract: A thermal capacitor component which includes, on a substrate, a stack of different layers defined in the form of a mesa terminating at its upper part in an electrical contact layer, which layer is coated with an electrically and thermally conducting layer surmounted by a heat sink element in contact with the conducting layer. The heat sink element has a plane shape. In addition, the component has at least one pad including another stack of layers which is also coated with an electrically and thermally conducting layer. The heat sink element is also in contact with the conducting layer of this stack so as to conduct the heat from the heat sink element into the substrate. Such a thermal capacitor may find application in the cooling of semiconductor components.

Abstract: The invention concerns a bipolar transistor with upper heterojunction comprising in particular stacked on a substrate: an emitter layer (EM); a base layer (BA), a collector layer (CO). In said transistor, the base-emitter junction surface is of smaller dimension than the base-collector junction surface and the material of the base layer has a lower electric conducting sensitivity to ion implantation than the electric conducting sensitivity of the material of the emitter layer to the same ion implant.

Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

Abstract: A semiconductor component that could be a power transistor type of component comprises mesa-structured elementary bipolar transistors. This component has a thick, metal heat sink of which a part (PI) takes the form of a bridge and a part is in contact with the substrate. The legs of the bridge lie on the entire unit constituted by the mesas. The heat sink made on the front face of the substrate may be connected to the rear face of the substrate comprising a ground plate. The discharging of the heat is thus appreciably fostered.

Abstract: Disclosed is a novel topology of monolithic, microwave amplifiers with high integration. This is a more compact topology, divided into a two-level or tree-like structure in which the division of the input signal is done firstly on each transistor Tij and, secondly, on each of the elementary transistors tijk of the transistors Tij. More specifically, the input line LE is divided into different basic lines li, each line li supplying lines lij distributed on either side of said lines li, a line lij then supplying a power transistor Tij. Application to microwave amplifiers.

Abstract: A bipolar transistor in which the emitter possesses a double "mesa" structure so as to achieve the maximum avoidance of the phenomena of electron/hole recombinations that have a deleterious effect on the current gain. The double mesa emitter can be made out of an alternation of materials M.sub.I /M.sub.II having different types of behavior with respect to a pair of etching methods. These materials may be GaInP and GaAs.

Abstract: Disclosed is a method for the etching of at least two layers of semiconductor materials having different natures, with a view to making a mesa for the self-alignment of the metallizations of a transistor. The heterojunction must comprise a first layer of a material containing As, which is etched by reactive ion etching, and a second layer of a material containing P which is etched chemically. Application to the making of HBT type vertical heterojunction transistors.

Abstract: The aim of the method is to prevent parasitic metallizations on the lateral walls of a raised pattern, which is used to self-align the electrode metallizations in a transistor. To this effect, a pair of semiconductor materials is introduced into the vertical pattern. These semiconductor materials react differently with respect to a pair of etching methods, so that a layer of one semiconductor material is etched to a greater extent than the other layer. The overhanging feature thus created interrupts the parasitic metallizations, if any, between the electrodes. The disclosed method can be applied to vertical structures.