Patents by Inventor Sylvain Dubois
Sylvain Dubois has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11222696Abstract: Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.Type: GrantFiled: June 30, 2020Date of Patent: January 11, 2022Assignee: Crossbar, Inc.Inventors: Mehdi Asnaashari, Hagop Nazarian, Christophe Sucur, Sylvain Dubois
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Integrating a resistive memory system into a multicore CPU die to achieve massive memory parallelism
Patent number: 11126550Abstract: Disclosed is a monolithic integrated circuit (IC) computing device with multiple independent process cores (multicore) and embedded, non-volatile resistive memory serving as system memory. The resistive system memory is fabricated above the substrate, and logic circuits embodying the process cores are fabricated on the substrate. In addition, access circuitry for operating on the resistive system memory, and circuitry embodying memory controllers, routing devices and other logic components is provided at least in part on the substrate. Large main memory capacities of tens or hundreds of gigabytes (GB) are provided and operable with many process cores, all on a single die. This monolithic integration provides close physical proximity between the process cores and main memory, facilitating significant memory parallelism, reduced power consumption, and eliminating off-chip main memory access requests.Type: GrantFiled: September 4, 2018Date of Patent: September 21, 2021Assignee: Crossbar, IncInventors: Donald Yeung, Bruce L. Jacob, Mehdi Asnaashari, Sylvain Dubois -
Patent number: 11127460Abstract: Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.Type: GrantFiled: September 27, 2018Date of Patent: September 21, 2021Assignee: Crossbar, Inc.Inventors: Mehdi Asnaashari, Hagop Nazarian, Christophe Sucur, Sylvain Dubois
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Patent number: 10699785Abstract: Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.Type: GrantFiled: September 27, 2018Date of Patent: June 30, 2020Assignee: CROSSBAR, INC.Inventors: Mehdi Asnaashari, Hagop Nazarian, Christophe Sucur, Sylvain Dubois
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Patent number: 10338826Abstract: Systems and methods embed a random-access non-volatile memory array in a managed-NAND system to execute the boot code or other time-sensitive applications. By embedding this random-access non-volatile memory in the managed-NAND system, either on the memory controller chip or as a separate chip within the managed-NAND system package, an application may be read with fast initial access time, alleviating the slow access time limitations of NAND Flash technology. Depending on the size of the application, the system may be configured to read the whole application content or only a time-critical portion from this embedded random-access non-volatile memory array.Type: GrantFiled: October 15, 2013Date of Patent: July 2, 2019Assignee: Cypress Semiconductor CorporationInventors: Sylvain Dubois, Stephan Rosner, Clifford A. Zitlaw
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Publication number: 20190103162Abstract: Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.Type: ApplicationFiled: September 27, 2018Publication date: April 4, 2019Inventors: Mehdi Asnaashari, Hagop Nazarian, Christophe Sucur, Sylvain Dubois
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Publication number: 20190102358Abstract: Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.Type: ApplicationFiled: September 27, 2018Publication date: April 4, 2019Inventors: Mehdi Asnaashari, Hagop Nazarian, Christophe Sucur, Sylvain Dubois
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Publication number: 20160025418Abstract: A heat exchanger is disclosed. The heat exchanger has a heat exchange assembly which defines first circulation channels for the circulation of a gas to be cooled and second circulation channels for the circulation of a cooling liquid, and two gas intake and gas outlet collectors, respectively, which are assembled on two open faces of the heat exchange assembly, respectively, in which the first circulation channels open. A first collector is crimped to the heat exchange assembly and a second collector is soldered or welded to the heat exchange assembly.Type: ApplicationFiled: March 12, 2014Publication date: January 28, 2016Applicant: VALEO SYSTEMES THERMIQUESInventors: Sébastien Devedeux, Julio Guerra, Denis Grosjean, Benjamin Ferlay, Laurent Odillard, Jéröme Blanchard, Nicolas Vallee, Yoann Naudin, Demetrio Onetti, Sylvain Dubois
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Patent number: 9047237Abstract: Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.Type: GrantFiled: August 3, 2012Date of Patent: June 2, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Qamrul Hasan, Clifford Zitlaw, Stephan Rosner, Sylvain Dubois
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Publication number: 20150106548Abstract: Systems and methods embed a random-access non-volatile memory array in a managed-NAND system to execute the boot code or other time-sensitive applications. By embedding this random-access non-volatile memory in the managed-NAND system, either on the memory controller chip or as a separate chip within the managed-NAND system package, an application may be read with fast initial access time, alleviating the slow access time limitations of NAND Flash technology. Depending on the size of the application, the system may be configured to read the whole application content or only a time-critical portion from this embedded random-access non-volatile memory array.Type: ApplicationFiled: October 15, 2013Publication date: April 16, 2015Inventors: Sylvain DUBOIS, Stephan Rosner, Clifford Zitlaw
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Publication number: 20140040587Abstract: Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.Type: ApplicationFiled: August 3, 2012Publication date: February 6, 2014Applicant: Spansion LLCInventors: Qamrul HASAN, Clifford ZITLAW, Stephan ROSNER, Sylvain DUBOIS
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Patent number: 8458429Abstract: An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).Type: GrantFiled: November 30, 2007Date of Patent: June 4, 2013Assignee: Texas Instruments IncorporatedInventors: Franck Dahan, Gilles Dubost, Sylvain Dubois
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Patent number: 8278980Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.Type: GrantFiled: May 31, 2012Date of Patent: October 2, 2012Assignee: Texas Instruments IncorporatedInventors: Gilles Dubost, Franck Dahan, Hugh Thomas Mair, Sylvain Dubois
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Publication number: 20120235716Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.Type: ApplicationFiled: May 31, 2012Publication date: September 20, 2012Inventors: GILLES DUBOST, Franck Dahan, Hugh Thomas Mair, Sylvain Dubois
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Patent number: 8207764Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.Type: GrantFiled: October 28, 2009Date of Patent: June 26, 2012Assignee: Texas Instruments IncorporatedInventors: Gilles Dubost, Franck Dahan, Hugh Thomas Mair, Sylvain Dubois
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Publication number: 20110224810Abstract: Systems (100) and methods (500) for controlling a household electronic device (HED). The HED (102, . . . , 114, 142) comprises a processing unit (302) configured to execute first device-control software operative for controlling the HED so that it performs a primary function using original values for a plurality of operating parameters. The methods involve receiving, at the HED, an active processing module (130, . . . , 140, 144, 146) configured to execute second device-control software. The second device-control software is operative for controlling the HED so that HED performs the primary function using a customized value for one or more of the operating parameters or performs a secondary function different than the primary function.Type: ApplicationFiled: March 12, 2010Publication date: September 15, 2011Applicant: Spansion LLCInventors: Sylvain Dubois, Joe Tom
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Publication number: 20110225327Abstract: Systems and methods (600) for controlling an electronic device (100) with an active processing module (308) having a first and second input/output interface (502, 504). The methods involve interfacing the active processing module and a computing device using the first input/output interface of the active processing module. Thereafter, the active processing module is programmed using a user interface of the computing device. The method also involves interfacing the active processing module and the electronic device using at least the second input/output interface of the active processing module. Subsequently, the operations of the electronic device are controlled using a processing unit (506) of the active processing module and/or a processing unit (424) of the electronic device.Type: ApplicationFiled: March 12, 2010Publication date: September 15, 2011Applicant: Spansion LLCInventors: JOE TOM, Sylvain Dubois
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Publication number: 20110095794Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.Type: ApplicationFiled: October 28, 2009Publication date: April 28, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Gilles Dubost, Franck Dahan, Hugh Thomas Mair, Sylvain Dubois
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Patent number: 7737986Abstract: The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.Type: GrantFiled: December 29, 2006Date of Patent: June 15, 2010Assignee: Texas Instruments IncorporatedInventors: Franck Seigneret, Sylvain Dubois, Jean Pierre Noel, Pierre-Yves J. Taloud
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Publication number: 20080162980Abstract: An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).Type: ApplicationFiled: November 30, 2007Publication date: July 3, 2008Inventors: Franck Dahan, Gilles Dubost, Sylvain Dubois