Abstract: An integrated circuit having an on-chip access right manager to grant or deny access to a memory segment to a peripheral device such as a CPU (Central Processing Unit), DSP (Digital Signal Processor) or DMA (Direct Memory Access) unit according to predetermined access rights upon reception of a read instruction from the peripheral device, and an on-chip lock connected to a memory data bus, the lock being controllable by the access right manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted. Upon reception of the read instruction from the peripheral device, the integrated circuit is configured to start both the process of setting, by the on chip memory, of either a logical one or a logical zero on each of the wires of the memo data bus, as well as the process of granting or refusing the access to the memory segment by the on-chip access right manager to the peripheral device.

Abstract: A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local clock signals from the reference clock signal for further provision to respective elements of the logic block. In such a circuit, a phase shift is introduced between a set of local clock signals of a first block and a set of local clock signals of a second block.

Abstract: The integrated circuit comprises: —an on-chip access right manager (40) to grant or deny access to a memory segment to a peripheral device (10) according to predetermined access rights upon reception of a read instruction from the peripheral device, —an on-chip lock (50) connected to a memory data bus, the lock being controllable by the access tight manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted.

Abstract: The frequency divider for high-frequency clock signal comprises: a shift register (8) having cells (10-13) for storing each bit of an initial word, said cells being series connected in a loop (14), and said shift register being capable of shifting each bit of the initial word from the cell in which it is stored to the next cell in the loop at a rate clocked by the high-frequency clock signal, and wherein an output terminal (6) for outputting a frequency-divided clock signal is connected to the output of one cell of the loop of series-connected cells.

Abstract: A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local clock signals from the reference clock signal for further provision to respective elements of the logic block. In such a circuit, a phase shift is introduced between a set of local clock signals of a first block and a set of local clock signals of a second block.

Abstract: The frequency divider for high-frequency clock signal comprises: a shift register (8) having cells (10-13) for storing each bit of an initial word, said cells being series connected in a loop (14), and said shift register being capable of shifting each bit of the initial word from the cell in which it is stored to the next cell in the loop at a rate clocked by the high-frequency clock signal, and wherein an output terminal (6) for outputting a frequency-divided clock signal is connected to the output of one cell of the loop of series-connected cells.