Patents by Inventor Sylvain Engels
Sylvain Engels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11616516Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: GrantFiled: May 25, 2022Date of Patent: March 28, 2023Assignee: STMICROELECTRONICS SAInventors: Pierre Dautriche, Sylvain Engels
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Publication number: 20220286149Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Inventors: Pierre Dautriche, Sylvain Engels
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Patent number: 11374597Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: GrantFiled: May 24, 2021Date of Patent: June 28, 2022Assignee: STMICROELECTRONICS SAInventors: Pierre Dautriche, Sylvain Engels
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Publication number: 20210399749Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: ApplicationFiled: May 24, 2021Publication date: December 23, 2021Inventors: Pierre Dautriche, Sylvain Engels
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Patent number: 11151287Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.Type: GrantFiled: December 7, 2018Date of Patent: October 19, 2021Assignees: STMICROELECTRONICS SA, INSTITUT POLYTECHNIQUE DE GRENOBLEInventors: Sophie Germain, Sylvain Engels, Laurent Fesquet
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Patent number: 10804885Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).Type: GrantFiled: October 16, 2019Date of Patent: October 13, 2020Assignee: STMicroelectronics SAInventors: Sylvain Engels, Alain Aurand, Etienne Maurin
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Publication number: 20200184110Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.Type: ApplicationFiled: December 7, 2018Publication date: June 11, 2020Inventors: Sophie Germain, Sylvain Engels, Laurent Fesquet
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Publication number: 20200112301Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).Type: ApplicationFiled: October 16, 2019Publication date: April 9, 2020Applicant: STMicroelectronics SAInventors: Sylvain ENGELS, Alain AURAND, Etienne MAURIN
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Patent number: 10505522Abstract: A standard cell layout for a flip-flop includes a flip-flop circuit and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the flip-flop. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in reset device (assertion of an initialization signal causing the flip-flop data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in set device (assertion of the initialization signal causing the flip-flop data output to be set).Type: GrantFiled: October 5, 2018Date of Patent: December 10, 2019Assignee: STMicroelectronics SAInventors: Sylvain Engels, Alain Aurand, Etienne Maurin
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Patent number: 9746863Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.Type: GrantFiled: December 4, 2015Date of Patent: August 29, 2017Assignee: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou, Julien Le Coz, Sylvain Engels
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Publication number: 20160370815Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.Type: ApplicationFiled: December 4, 2015Publication date: December 22, 2016Applicant: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou, Julien Le Coz, Sylvain Engels
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Patent number: 8819615Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.Type: GrantFiled: September 16, 2013Date of Patent: August 26, 2014Assignee: STMicroelectronics SAInventors: Julien Le Coz, Sylvain Engels, Alain Tournier
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Patent number: 8710917Abstract: A method for controlling the power supply of an integrated circuit, the power supply comprising a power supply unit powered by a main voltage and possessing several transistor groups, comprising turning on in succession at least two transistor groups in order to deliver, as an output from each group, to at least one part of the integrated circuit, an elementary supply voltage derived from the main voltage, characterized in that the method comprises at least one elementary power phase for supplying power to said at least one part of the integrated circuit, wherein the phase comprises defining voltage thresholds respectively associated with the transistor groups, turning on a first transistor group, the first group delivering a first elementary supply voltage and turning on at least one second group when the first elementary supply voltage is higher than or equal to the voltage threshold associated with the second group.Type: GrantFiled: August 17, 2012Date of Patent: April 29, 2014Assignee: STMicroelectronics SAInventors: Nicolas L'Hostis, Sylvain Engels, Fabrice Blisson, ClaireMarie Lachaud
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Publication number: 20140089885Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.Type: ApplicationFiled: September 16, 2013Publication date: March 27, 2014Applicant: STMICROELECTRONICS SAInventors: Julien Le Coz, Sylvain Engels, Alain Tournier
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Publication number: 20130300458Abstract: A circuit for detecting a time skew, including: at least two comparators; a first set of paths respectively connecting a first source of a first signal to said comparators; and a second set of paths respectively connecting a second source of a second signal to said comparators, each comparator detecting a possible skew between said first and second signals.Type: ApplicationFiled: September 14, 2012Publication date: November 14, 2013Applicant: STMICROELECTRONICS SAInventors: Thomas le Huche, Sylvain Engels
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Patent number: 8570096Abstract: A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.Type: GrantFiled: September 14, 2011Date of Patent: October 29, 2013Assignee: STMicroelectronics SAInventors: Julien Le Coz, Alexandre Valentian, Philippe Flatresse, Sylvain Engels
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Patent number: 8436652Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.Type: GrantFiled: June 2, 2011Date of Patent: May 7, 2013Assignee: STMicroelectronics, SAInventor: Sylvain Engels
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Publication number: 20130043936Abstract: A method for controlling the power supply of an integrated circuit, the power supply comprising a power supply unit powered by a main voltage and possessing several transistor groups, comprising turning on in succession at least two transistor groups in order to deliver, as an output from each group, to at least one part of the integrated circuit, an elementary supply voltage derived from the main voltage, characterized in that the method comprises at least one elementary power phase for supplying power to said at least one part of the integrated circuit, wherein the phase comprises defining voltage thresholds respectively associated with the transistor groups, turning on a first transistor group, the first group delivering a first elementary supply voltage and turning on at least one second group when the first elementary supply voltage is higher than or equal to the voltage threshold associated with the second group.Type: ApplicationFiled: August 17, 2012Publication date: February 21, 2013Applicant: STMicroeletronics SAInventors: Nicolas L'Hostis, Sylvain Engel, Fabrice Blisson, ClaireMarie Lachaud
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Patent number: 8294508Abstract: An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases.Type: GrantFiled: January 7, 2011Date of Patent: October 23, 2012Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Robin Wilson, Sylvain Engels, Eric Balossier
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Publication number: 20120062313Abstract: A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.Type: ApplicationFiled: September 14, 2011Publication date: March 15, 2012Applicant: STMicroelectronics SAInventors: Julien LE COZ, Alexandre Valentian, Philippe Flatresse, Sylvain Engels