Patents by Inventor Sylvain Engels

Sylvain Engels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804885
    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • Publication number: 20200184110
    Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Sophie Germain, Sylvain Engels, Laurent Fesquet
  • Publication number: 20200112301
    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).
    Type: Application
    Filed: October 16, 2019
    Publication date: April 9, 2020
    Applicant: STMicroelectronics SA
    Inventors: Sylvain ENGELS, Alain AURAND, Etienne MAURIN
  • Patent number: 10505522
    Abstract: A standard cell layout for a flip-flop includes a flip-flop circuit and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the flip-flop. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in reset device (assertion of an initialization signal causing the flip-flop data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in set device (assertion of the initialization signal causing the flip-flop data output to be set).
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • Patent number: 10451750
    Abstract: The invention concerns a scintillation detector with which high count rates and/or high resolutions are possible. The scintillator of the claimed scintillation detector is formed from pixels (2), which are separated from each other by interstices (4). Alternatively or additionally, the surface of the scintillator is divided by grooves into pixels (2). Such a structure enables not only a particularly high resolution. When multiple detector modules are used, it also allows high count rates in the range of roughly 20 MHz.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 22, 2019
    Assignees: Forschungszentrum Jülich GmbH, Commissariat á l'Energie Atomique et aux Energies (CEA), Integrated Detector Electronics AS, Legal Division European Spallation Source ERIC
    Inventors: Sebastian Jaksch, Henrich Frielinghaus, Ralf Engels, Günter Kemmerling, Kalliopi Kanaki, Richard Hall-Wilton, Sylvain Désert, Codin Gheorghe
  • Patent number: 9746863
    Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: August 29, 2017
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou, Julien Le Coz, Sylvain Engels
  • Publication number: 20160370815
    Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.
    Type: Application
    Filed: December 4, 2015
    Publication date: December 22, 2016
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou, Julien Le Coz, Sylvain Engels
  • Patent number: 8819615
    Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 26, 2014
    Assignee: STMicroelectronics SA
    Inventors: Julien Le Coz, Sylvain Engels, Alain Tournier
  • Patent number: 8710917
    Abstract: A method for controlling the power supply of an integrated circuit, the power supply comprising a power supply unit powered by a main voltage and possessing several transistor groups, comprising turning on in succession at least two transistor groups in order to deliver, as an output from each group, to at least one part of the integrated circuit, an elementary supply voltage derived from the main voltage, characterized in that the method comprises at least one elementary power phase for supplying power to said at least one part of the integrated circuit, wherein the phase comprises defining voltage thresholds respectively associated with the transistor groups, turning on a first transistor group, the first group delivering a first elementary supply voltage and turning on at least one second group when the first elementary supply voltage is higher than or equal to the voltage threshold associated with the second group.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 29, 2014
    Assignee: STMicroelectronics SA
    Inventors: Nicolas L'Hostis, Sylvain Engels, Fabrice Blisson, ClaireMarie Lachaud
  • Publication number: 20140089885
    Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 27, 2014
    Applicant: STMICROELECTRONICS SA
    Inventors: Julien Le Coz, Sylvain Engels, Alain Tournier
  • Publication number: 20130300458
    Abstract: A circuit for detecting a time skew, including: at least two comparators; a first set of paths respectively connecting a first source of a first signal to said comparators; and a second set of paths respectively connecting a second source of a second signal to said comparators, each comparator detecting a possible skew between said first and second signals.
    Type: Application
    Filed: September 14, 2012
    Publication date: November 14, 2013
    Applicant: STMICROELECTRONICS SA
    Inventors: Thomas le Huche, Sylvain Engels
  • Patent number: 8570096
    Abstract: A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: October 29, 2013
    Assignee: STMicroelectronics SA
    Inventors: Julien Le Coz, Alexandre Valentian, Philippe Flatresse, Sylvain Engels
  • Patent number: 8436652
    Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: May 7, 2013
    Assignee: STMicroelectronics, SA
    Inventor: Sylvain Engels
  • Publication number: 20130043936
    Abstract: A method for controlling the power supply of an integrated circuit, the power supply comprising a power supply unit powered by a main voltage and possessing several transistor groups, comprising turning on in succession at least two transistor groups in order to deliver, as an output from each group, to at least one part of the integrated circuit, an elementary supply voltage derived from the main voltage, characterized in that the method comprises at least one elementary power phase for supplying power to said at least one part of the integrated circuit, wherein the phase comprises defining voltage thresholds respectively associated with the transistor groups, turning on a first transistor group, the first group delivering a first elementary supply voltage and turning on at least one second group when the first elementary supply voltage is higher than or equal to the voltage threshold associated with the second group.
    Type: Application
    Filed: August 17, 2012
    Publication date: February 21, 2013
    Applicant: STMicroeletronics SA
    Inventors: Nicolas L'Hostis, Sylvain Engel, Fabrice Blisson, ClaireMarie Lachaud
  • Patent number: 8294508
    Abstract: An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: October 23, 2012
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Robin Wilson, Sylvain Engels, Eric Balossier
  • Publication number: 20120062313
    Abstract: A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 15, 2012
    Applicant: STMicroelectronics SA
    Inventors: Julien LE COZ, Alexandre Valentian, Philippe Flatresse, Sylvain Engels
  • Publication number: 20110298491
    Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 8, 2011
    Applicant: STMicroelectronics SA
    Inventor: Sylvain Engels
  • Publication number: 20110199149
    Abstract: An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases.
    Type: Application
    Filed: January 7, 2011
    Publication date: August 18, 2011
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Robin Wilson, Sylvain Engels, Eric Balossier