Abstract: A microcontroller configured to provide secure integrity checking of code or data stored in the microcontroller is provided. The microcontroller may include a processor, memory devices defining a microcontroller memory space, a security attribution unit defining secure memory region(s) and non-secure memory region(s) in the memory space, integrity check tables indicating storage locations of various code within the microcontroller memory space, and an integrity checking unit. The integrity checking unit may be configured to receive an integrity check request for checking the integrity of a first piece of code stored in the microcontroller memory space, access a first integrity check table that indicates a storage location of the first piece of code, determine whether the first integrity check table and first piece of code are stored in the same memory region; and determine whether to perform the requested integrity check based at least on this determination.

Abstract: A microcontroller configured to provide secure integrity checking of code or data stored in the microcontroller is provided. The microcontroller may include a processor, memory devices defining a microcontroller memory space, a security attribution unit defining secure memory region(s) and non-secure memory region(s) in the memory space, integrity check tables indicating storage locations of various code within the microcontroller memory space, and an integrity checking unit. The integrity checking unit may be configured to receive an integrity check request for checking the integrity of a first piece of code stored in the microcontroller memory space, access a first integrity check table that indicates a storage location of the first piece of code, determine whether the first integrity check table and first piece of code are stored in the same memory region; and determine whether to perform the requested integrity check based at least on this determination.

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

Abstract: Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract: Systems and techniques for hot-plugging debugger capabilities are described. A described integrated circuit device includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface.

Abstract: Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.

Abstract: Systems and techniques for hot-plugging debugger capabilities are described. A described integrated circuit device includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface.

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract: A method for optimising writing by a master block into an interfacing device between the master block and a slave block. The method includes a step for transformation of a code into assembler language, done before the code in machine language is obtained and including the following steps: transformation of all static unit writes comprising more than one word from the assembler language code into one-word static unit writes; search for each set of N successive static one-word unit writes; replace at least one set of N successive static one-word unit writes by one static unit N-word write of, in the assembler language code, where N is an integer greater than or equal to 2.

Abstract: The disclosure relates to a reverse Polish notation processing device making it possible to execute a set of instructions and implementing management of a stack whose size is variable. The device includes a storage device including a random access memory; a device for managing a stack pointer, which is a physical address, in said random access memory, associated with a reference stage of the stack; and a device for managing reference element pointer(s), which is a physical address, in said random access memory, associated with one reference element among elements of a given table contained in the stack. The processing device can execute at least one table-handling instruction with respect to the reference element pointer(s).

Abstract: The disclosure relates to a reverse Polish notation processing device, allowing execution of a set of instructions wherein each instruction comprises N operands at most, where N?1. The device implements management of a stack whose size is variable. Such a device includes: a storage device including a random access memory and a cache memory; a stack pointer managing device for managing a stack pointer; and a contents managing device for managing the contents of the stages of the stack, according to said stack pointer. For each of the first N stages of the stack, the content of said stage is stored in the cache memory, and for each of the other stages of the stack, the content of said stage is stored in the random access memory; allowing to manage content overflows from the cache memory towards the random access memory, and vice-versa.

Abstract: An interfacing device (23) of the type enabling one-way interfacing between a master unit (21) and a slave unit (22), includes: a memory plane managed according to a “first in, first out” mode, with write and read pointers, and making it possible to store words coming from the master unit, via an input bus (FIFODin); a bank of output registers capable of containing words read in the memory plane and providing an output signal (FIFODout) capable of being read by the slave unit; a mechanism configured to receive read requests (FIFORdRq=1) coming from the slave unit and write requests (FIFOWr=1) coming from the master unit, each read request requiring the reading of a word group.