Abstract: A steering wheel having a steering wheel body (10) having a first force transmitting component, and a horn actuation element. The horn actuation element having a horn actuation surface (23) and having a second force transmitting component. A load cell (30) is provided having a sensitive element that changes at least one of its electrical properties in response to a compression force. The sensitive element placed between the first and second force transmitting components. At least one elastically deformable element is provided between the steering wheel body (10) and the horn actuation element. When a pushing force is applied to the horn actuation surface (23) the force applied to the sensitive element changes.

Abstract: A method and an apparatus for generating a horn actuation signal. A load cell is placed inside a steering wheel, which changes its resistance when being stressed or deformed by a force transmitting part of the steering wheel. An actual voltage (Va) depending on the resistance of the load cell is measured and the horn actuation signal is generated based on the measurement of the actual voltage (Va). The actual voltage (Va) depends additionally to the resistance of the load cell and on an adjustable voltage (Vad) generated by an adjustable voltage generation unit. Additionally, the result of the measurement of the actual voltage (Va) is permanently compared to a defined value, and the adjustable voltage (Vad) is adjusted in response to the difference between the result of the measurement of the actual voltage (Va) and the defined value at least as long as no horn actuation signal is generated, such that closed circuit for controlling the actual voltage (Va) is provided.

Abstract: A method and an apparatus for generating a horn actuation signal. A load cell is placed inside a steering wheel, which changes its resistance when being stressed or deformed by a force transmitting part of the steering wheel. An actual voltage (Va) depending on the resistance of the load cell is measured and the horn actuation signal is generated based on the measurement of the actual voltage (Va). The actual voltage (Va) depends additionally to the resistance of the load cell and on an adjustable voltage (Vad) generated by an adjustable voltage generation unit. Additionally, the result of the measurement of the actual voltage (Va) is permanently compared to a defined value, and the adjustable voltage (Vad) is adjusted in response to the difference between the result of the measurement of the actual voltage (Va) and the defined value at least as long as no horn actuation signal is generated, such that closed circuit for controlling the actual voltage (Va) is provided.

Abstract: There is described a double stage sense amplifier (4) in bipolar technology achieving very high speed operation without saturation or connection problems. For each memory cell column of the computer member system (1), a first stage or column sense stage (4.1) amplifies the differential input signal (V) produced on the pair of bit lines (BLL, BLR) according to the information read from one CMOS memory cell of the memory cell array (3.1) to provide a first differential output signal (V1) available at output terminals (10.1, 10.2). The output terminals of all the first stage (4.1 to 4.n) are connected to a first-data out bus comprised of the data lines (DLC1, DLT1). A second stage or final stage (4') amplifies the first differential output signal developed on the data lines to provide a second differential output signal (V2) at output terminals (17.1, 17.2). The second stage of the common base amplifier type is comprised of two transistors (T9, T10).

Abstract: A two stage address decoder circuit (AD) for 1/64 decode operation is disclosed which operates at high speed with low power consumption. Briefly stated, the circuit includes a first stage comprised of two predecoder circuits operable to develop predecoded output signals in response to input address signals and corresponding inverted address signals. Each predecoder circuit consists of a lower power high speed Differential Cascode Current Switch tree with its associated current source. The second or final decode stage is comprised of a plurality of final decoding circuits. Each final circuit consisting of a 2 way OR gate dynamically activated through a switched current source. The inputs of the 2 way OR gate are connected to one pair of the predecoded output signals. Final decoder circuits provide final decoded output signals which drive the word lines of a memory cell array.