Abstract: Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

Abstract: An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

Abstract: A method may include forming a plurality of multilayer cores wherein each multilayer core comprises a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material, patterning each layer of metal in the plurality of multilayer cores to form wiring traces in each layer of metal, embedding a solder element in at least one sheet of a plurality of sheets of uncured dielectric material, wherein the solder element having a melting point temperature within a temperature range of a curing temperature of the uncured dielectric material, forming a printed circuit board by alternately stacking the plurality of multilayer cores with the plurality of sheets of uncured dielectric material between each multilayer core, laminating the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material and melting of the solder element.

Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.

Abstract: A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.

Abstract: A method may include forming a plurality of multilayer cores wherein each multilayer core comprises a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material, patterning each layer of metal in the plurality of multilayer cores to form wiring traces in each layer of metal, embedding a solder element in at least one sheet of a plurality of sheets of uncured dielectric material, wherein the solder element having a melting point temperature within a temperature range of a curing temperature of the uncured dielectric material, forming a printed circuit board by alternately stacking the plurality of multilayer cores with the plurality of sheets of uncured dielectric material between each multilayer core, laminating the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material and melting of the solder element.

Abstract: An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.

Abstract: A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.

Abstract: A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased resistivity.

Abstract: A method including forming a first solder bump on a chip, the first solder bump made of a first alloy, and forming a second solder bump on a chip, the second solder bump made of a second alloy, where the first alloy has a different alloy concentration and is different from the second alloy.

Abstract: A method including identifying a first connection location on a chip having a first connection type and a second connection location on the chip having a second connection type, applying a first solder alloy to the first connection location, heating the first solder alloy to a temperature sufficient to cause the first solder alloy to reflow, applying a second solder alloy to the second connection location, and heating the second solder alloy to a temperature sufficient to cause the second solder alloy to reflow.

Abstract: A method including forming a first solder bump on a chip, the first solder bump made of a first alloy, and forming a second solder bump on a chip, the second solder bump made of a second alloy, where the first alloy has a different alloy concentration and is different from the second alloy.

Abstract: A method of sorting laminates includes characterizing first shapes of laminates from measurements taken of each, assembling the laminates to derive a first relationship between the first shapes and yield loss, characterizing second shapes of the laminates from a reduced number of the measurements to derive a second relationship between the second shapes and yield loss, analyzing a change in the derived relationships to determine a least number of the measurements necessary for achieving the yield loss and sorting supplied laminates in accordance with a characterized shape of each, which is obtained from the least number of the measurements taken for each supplied laminate.

Abstract: A method for forming coreless flip chip ball grid array (FCBGA) substrates comprising the steps of sequentially depositing a pair of laminates, each having a plurality of insulated metallization layers simultaneously respectively on each side of a temporary carrier substrate, and then removing the temporary carrier to separate the pair of laminates, so that each laminate has an outer ball grid metal pad array, and during the depositing of the pair of laminates on the carrier substrate, further depositing a supporting layer of dielectric material enclosing the metal pad array, wherein said supporting layers of dielectric material provides structural support for each of the laminates after the separation.

Abstract: A method for forming coreless flip chip ball grid array (FCBGA) substrates comprising the steps of sequentially depositing a pair of laminates, each having a plurality of insulated metallization layers simultaneously respectively on each side of a temporary carrier substrate, and then removing the temporary carrier to separate the pair of laminates, so that each laminate has an outer ball grid metal pad array, and during the depositing of the pair of laminates on the carrier substrate, further depositing a supporting layer of dielectric material enclosing the metal pad array, wherein said supporting layers of dielectric material provides structural support for each of the laminates after the separation.

Abstract: A method of sorting laminates includes characterizing first shapes of laminates from measurements taken of each, assembling the laminates to derive a first relationship between the first shapes and yield loss, characterizing second shapes of the laminates from a reduced number of the measurements to derive a second relationship between the second shapes and yield loss, analyzing a change in the derived relationships to determine a least number of the measurements necessary for achieving the yield loss and sorting supplied laminates in accordance with a characterized shape of each, which is obtained from the least number of the measurements taken for each supplied laminate.

Abstract: A method for analyzing the warpage of organic laminates used in flip chip packages includes collecting warpage data and layer thickness data for several laminates. A principal components analysis may then be performed on the thickness data to calculate orthogonal basis vectors to re-express the thickness data in a different basis. The thickness data may then be projected onto the orthogonal basis vectors. A linear model may be generated that expresses the warpage data for each laminate in terms of the projection of corresponding thickness data onto the orthogonal basis vectors, each projection multiplied by a weight. These weights may then be analyzed to determine the contribution of each orthogonal basis vector to the variance of the warpage data. The contribution and structure of each orthogonal basis vector may then be interpreted to estimate the importance of each layer or combination of layers in contributing to the laminate warpage.