Abstract: A method for locating a failing latch in a defective shift register having P latches connected in series fabricated in an integrated circuit chip. The chip is depassivated to expose its upper metalized layer, and it is in the chamber of a scanning electron microscope (SEM) having sharp voltage contrast capabilities. Clock signals are generated to properly exercise the shift register. A string of N latches, wherein 1≦N≦P, typically N=P/2 is first selected and the stimuli are applied to the latches to allow the output net of the last latch of the string to toggle at a frequency of about 1 Hz. The SEM beam is focused on the area which encompasses the last latch, so that, if the latch output net blinks on the SEM screen, the string under observation is deemed to be good. Then, another, more extended string is selected and the above procedure is repeated.