Abstract: A system, method, apparatus and computer readable medium for hierarchical speech recognition resolution. The method of hierarchical speech recognition resolution on a platform includes receiving a speech stream from a microphone. The speech stream is resolved using a lowest possible level automatic speech recognition (ASR) engine of multi-level ASR engines. The selection of the lowest possible level ASR engine is based on policies defined for the platform. If resolution of the speech stream is rated less than a predetermined confidence level, the resolution of the speech stream is pushed to a next higher-level ASR engine of the multi-level ASR engines until the resolution of the speech stream meets the predetermined confidence level without violating one or more policies.

Abstract: A system, method, apparatus and computer readable medium for hierarchical speech recognition resolution. The method of hierarchical speech recognition resolution on a platform includes receiving a speech stream from a microphone. The speech stream is resolved using a lowest possible level automatic speech recognition (ASR) engine of multi-level ASR engines. The selection of the lowest possible level ASR engine is based on policies defined for the platform. If resolution of the speech stream is rated less than a predetermined confidence level, the resolution of the speech stream is pushed to a next higher-level ASR engine of the multi-level ASR engines until the resolution of the speech stream meets the predetermined confidence level without violating one or more policies.

Abstract: A system, apparatus, method and article to switch between video display modes are described. The apparatus may include a graphics device to switch between a progressive mode and an interlaced mode to display media information using a single pixel clock frequency for both modes. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention is a technique to map pins on an interface connector to signals for a digital display. A first group of signal traces maps transmitter differential pairs pins in a first group of lanes on the interface connector compatible with a first interface standard to video output points corresponding to video output signals of a first video port compatible with a second interface standard. A second group of signal traces maps presence detect pins in the first group of lanes on the interface connector to control signal points corresponding to control signals of the first video port compatible with the second interface standard. A third group of signal traces maps receiver differential pairs pins in the first group of lanes on the interface connector to video input points corresponding to video input signals of the first video port compatible with the second interface standard.

Abstract: A number of pixels are received at a pixel rate that corresponds to a lower data transfer rate. The received pixels are delivered for display on a display device, over an interface that operates at a higher data transfer rate. These pixels are delivered as part of a stream that includes one or more codes that have been inserted between each adjacent pair of pixels so that the pixels in the stream are still delivered at the pixel rate. Other embodiments are also described and claimed.

Abstract: Techniques to switch between video display modes are described. An apparatus may include a graphics device to generate first synchronized timing signals with a first phase differential to indicate a first display mode for first display data, and to generate second synchronized timing signals with a second phase differential to indicate a second display mode for second display data. Other embodiments are described and claimed.