Patents by Inventor Sylvia Patterson

Sylvia Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for cross simulation data sharing to facilitate higher resolution data measurements for complex designs
    Publication number: 20060190230
    Abstract: A method and apparatus is presented for performing simulation of complex circuits. A circuit is simulated in a fast simulator. State information, which is the output of the fast simulator, is translated in a translator and then the circuit is simulated in a slow simulator. In one embodiment, the circuit is modeled in a digital format in the fast simulator and modeled in an analog format in the slow simulator.
    Type: Application
    Filed: February 24, 2005
    Publication date: August 24, 2006
    Inventors: Sylvia Patterson, Robert Zimmer
  • SERDES cooperates with the boundary scan test technique
    Patent number: 6653957
    Abstract: Improvement in the transmission of Boundary Scan Test mode data may be achieved through the assignment of boundary scan test mode traffic to selected bit patterns that facilitate clock recovery and frame alignment in the serial channel. The encoding of boundary scan test traffic as such may be achieved through either multiplexed transmission to the serializer/deserializer (SERDES) alongside a regular channel encoder or incorporated into the channel encoder.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: November 25, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Sylvia Patterson, Jeff Rearick