Abstract: A Switch Fabric system comprising at least one Switch Fabric subsystem (100, 200) further including a set of Switch cores elements (111, 112, 121, 122) that are mounted in a port expansion permitting attachment of at least a first and second sets of Protocol Adapters (1, 2) under a routing control process. A Primary Switch controller (PSC) has a complete knowledge of the topology of the switch, e.g., the number of subsystems, the nature of the port expansion etc., while each Secondary Switch Controller only has a limited knowledge of that topology. One particular Switch Core (111, 211) which has a full-duplex communication capability in each Subsystem is assigned the key function to interface communication between the PSC and the other SSC in a same Switch Fabric Subsystem.

Abstract: A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell.

Abstract: A switching system having at least two switch fabrics. Each fabric has a switch core and a set of SCAL (Switch Core Access Layer) receive and transmit elements. The switch cores are preferably located in the same physical area but the SCALs may be distributed in different physical areas. Port Adapters distributed at different physical areas are connected to the switch fabrics via a particular SCAL element so that each switch core can receive cells from any port adapter and conversely any port adapter may receive data from either switch core. Control logic assigns a particular switch core to one port adapter for normal operations while reserving the other switch core for use when the first core is out of service. Each switch core has a mask mechanism which uses the value in a mask register to alter a bitmap value which controls the routing process. The mask registers in the two switch cores are loaded with complementary values.

Abstract: A fault tolerant switching architecture is provided with two separate switch fabrics each having a switch cure located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element has both a SCAL receive element and a SCAL transmit element for access to a corresponding input and output port of the swatch core. A set of port adapters is distributed at different physical areas, with each connected switch fabrics via a particular SCAL element so that each switch core receives the sequence of cells coming from any port adapter and conversely any port adapter may receive cells from either one of the switch cores. Each switch fabric can detect an internal breakdown condition occurring in one of its element and send an error control signal to the peer element located in the other switch fabric.

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit includes means for introducing at least one extra byte to every cell. The extra byte is reserved for carrying a routing header for controlling the switching structure in a first step, and then for use by the PINT circuit when the cell will be received by the transmit part in a second step. The transmit part of each PINT circuit comprises a control module that receives all the cells generated at the corresponding output port and controls whether to discard the cell based on the value of the extra byte.

Abstract: Multiple operating configurations in data circuit terminating equipment (DCE) are enabled through multiple queues stored in a random access memory and which are loaded with bits and characters coming either from data terminating equipment (DTE) or the telecommunications line. The DSP processor stores bits provided by a transmit circuit in a first queue, determines characters from the bits stored in the first queue based on a first transmission protocol and stores the characters in a second queue. A third queue is used by a control processor to store characters to be transmitted to a remote DCE. The DSP processor determines bits to be transmitted from the characters stored in a third queue based on a second transmission protocol, and stores those bits in a fourth queue. When the DCE is operating in a synchronous mode, the DSP processor determines PCM words for transmission based on the contents of the second queue and stores them in a fifth queue for transmission.