Patents by Inventor Sylvie Mignot

Sylvie Mignot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9478663
    Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Yi Qi, Sylvie Mignot
  • Patent number: 9437475
    Abstract: A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: September 6, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Maud Vinet, Sylvie Mignot, Romain Wacquez
  • Publication number: 20160126353
    Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 5, 2016
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Yi Qi, Sylvie Mignot
  • Patent number: 9299775
    Abstract: Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Steven Bentley, Kejia Wang, Sylvie Mignot, Shurong Liang
  • Patent number: 9287130
    Abstract: A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: March 15, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Xiuyu Cai, Ajey Poovannummoottil Jacob, Ruilong Xie, Bruce Doris, Kangguo Cheng, Jason R. Cantone, Sylvie Mignot, David Moreau, Muthumanickam Sankarapandian, Pierre Morin, Su Chen Fan, Kisik Choi, Murat K. Akarvardar
  • Publication number: 20150303249
    Abstract: Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Steven Bentley, Kejia Wang, Sylvie Mignot, Shurong Liang
  • Publication number: 20150294904
    Abstract: A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.
    Type: Application
    Filed: November 8, 2012
    Publication date: October 15, 2015
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Maud Vinet, Sylvie Mignot, Romain Wacquez