Patents by Inventor Sylwester Milewski

Sylwester Milewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11422188
    Abstract: The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 23, 2022
    Assignee: Siemens Industry Software Inc
    Inventors: Yu Huang, Janusz Rajski, Sylwester Milewski
  • Patent number: 11150299
    Abstract: A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 19, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Janusz Rajski, Yu Huang, Sylwester Milewski, Jerzy Tyszer
  • Patent number: 10996273
    Abstract: Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern. The hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation. Activation probabilities and observation probabilities are then determined for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates. Finally, test patterns are generated based on the activation probabilities and the observation probabilities.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: May 4, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Sylwester Milewski, Janusz Rajski, Yu Huang
  • Publication number: 20210018563
    Abstract: A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.
    Type: Application
    Filed: March 21, 2019
    Publication date: January 21, 2021
    Inventors: Janusz Rajski, Yu Huang, Sylwester Milewski, Jerzy Tyszer
  • Patent number: 10509072
    Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
  • Publication number: 20190293718
    Abstract: Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern. The hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation. Activation probabilities and observation probabilities are then determined for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates. Finally, test patterns are generated based on the activation probabilities and the observation probabilities.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 26, 2019
    Inventors: Sylwester Milewski, Janusz Rajski, Yu Huang
  • Publication number: 20190293717
    Abstract: The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 26, 2019
    Inventors: Yu Huang, Janusz Rajski, Sylwester Milewski
  • Patent number: 10120029
    Abstract: Aspects of the disclosed technology relate to low power testing. A low power test circuit comprises a test stimulus source, a controller; and a grouping and selection unit. The grouping and selection unit has inputs coupled to the test stimulus source and the controller and has outputs coupled to a plurality of scan chains. The grouping and selection unit is configured to dynamically group scan chains in the plurality of scan chains into a plurality of scan chain groups and to selectively output either original test pattern values generated by the test stimulus source or a constant value to each scan chain group in the plurality of scan chain groups based on control signals received from the controller.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: November 6, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Sylwester Milewski, Grzegorz Mrugalski, Jerzy Tyszer
  • Publication number: 20180252768
    Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.
    Type: Application
    Filed: January 30, 2018
    Publication date: September 6, 2018
    Inventors: Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
  • Publication number: 20150323597
    Abstract: Aspects of the disclosed technology relate to low power testing. A low power test circuit comprises a test stimulus source, a controller; and a grouping and selection unit. The grouping and selection unit has inputs coupled to the test stimulus source and the controller and has outputs coupled to a plurality of scan chains. The grouping and selection unit is configured to dynamically group scan chains in the plurality of scan chains into a plurality of scan chain groups and to selectively output either original test pattern values generated by the test stimulus source or a constant value to each scan chain group in the plurality of scan chain groups based on control signals received from the controller.
    Type: Application
    Filed: May 12, 2015
    Publication date: November 12, 2015
    Inventors: Janusz Rajski, Sylwester Milewski, Grzegorz Mrugalski, Jerzy Tyszer