Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method includes forming an oxidized portion of an initial gate structure and a sacrificial gate layer, and further includes removing the oxidized portion of the initial gate structure and the sacrificial gate layer to form a transistor device. In an exemplary embodiment, the method further includes subjecting a patterned gate layer to an etch to form the initial gate structure and the sacrificial layer. In an advantageous embodiment, the gate layer is patterned having a width greater than a predetermined design width.