Abstract: Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state.

Abstract: A connection scheme is used to selectively connect a dither capacitor included in a calibrated stage of a pipeline analog-to-digital converter (ADC) in a way that reduces the output voltage swing of the stage. A first terminal of the dither capacitor is coupled to an input of the amplifier. A second terminal of the dither capacitor is coupled to either a first or second reference voltage dependent on a bit value in a Pseudo-Random Binary Sequence (PRBS) if a voltage received by the stage is within a first voltage range. If the stage received voltage is within a second range, the second terminal is coupled to the first reference voltage independent of the PRBS. If the stage received voltage is within a third range, the second terminal is coupled to the second reference voltage independent of the PRBS.

Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

Abstract: Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

Abstract: An electronic device is provided which comprises a plurality of processing units (IP1-IP6), a network-based interconnect (N) coupled to the processing units (IP1-IP6) and at least one monitoring unit (P1, P2) for monitoring a data flow of at least one first communication path between the processing units (IP1-IP6) and for forwarding monitoring results at least temporarily via at least two separate communication paths (MC1, MC2).

Abstract: Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points.

Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a method implemented on a data processing system for circuit synthesis comprises determining a Read Only Memory (ROM) of a design of a circuit, the ROM having predefined data when the circuit is initialized, and automatically generating an initialization circuit and a Random Access Memory (RAM) to implement the ROM, the initialization circuit to load the predefined data into the RAM when the circuit is initialized.