Patents by Inventor Syo Fukata
Syo Fukata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935784Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.Type: GrantFiled: June 11, 2021Date of Patent: March 19, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Fumitaka Amano, Yusuke Osawa, Kensuke Ishikawa, Mitsuteru Mushiga, Motoki Kawasaki, Shinsuke Yada, Masato Miyamoto, Syo Fukata, Takashi Kashimura, Shigehiro Fujino
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Deposition apparatus including an off-axis lift-and-rotation unit and methods for operating the same
Patent number: 11598005Abstract: A deposition chamber includes a vacuum enclosure, an electrostatic chuck having a flat top surface located within a vacuum enclosure, a lift-and-rotation unit extending through or laterally surrounding the electrostatic chuck at a position that is laterally offset from a vertical axis passing through a geometrical center of the electrostatic chuck, a gas supply manifold configured to provide influx of gas into the vacuum enclosure, and a pumping port connected to the vacuum enclosure.Type: GrantFiled: May 7, 2020Date of Patent: March 7, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Shoichi Murakami, Shigeru Nakatsuka, Syo Fukata, Yusuke Osawa, Shigehiro Fujino, Masaaki Higashitani -
Patent number: 11551961Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.Type: GrantFiled: May 6, 2020Date of Patent: January 10, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Shoichi Murakami, Shigeru Nakatsuka, Syo Fukata, Yusuke Osawa, Shigehiro Fujino, Masaaki Higashitani
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Patent number: 11538708Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.Type: GrantFiled: May 6, 2020Date of Patent: December 27, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Shoichi Murakami, Shigeru Nakatsuka, Syo Fukata, Yusuke Osawa, Shigehiro Fujino, Masaaki Higashitani
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Publication number: 20220399232Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.Type: ApplicationFiled: June 11, 2021Publication date: December 15, 2022Inventors: Fumitaka AMANO, Yusuke OSAWA, Kensuke ISHIKAWA, Mitsuteru MUSHIGA, Motoki KAWASAKI, Shinsuke YADA, Masato MIYAMOTO, Syo FUKATA, Takashi KASHIMURA, Shigehiro FUJINO
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Publication number: 20210391154Abstract: An anisotropic etch apparatus contains an electrostatic chuck located in a vacuum enclosure and including a lower electrode, an upper electrode overlying the lower electrode and located in the vacuum enclosure, a main radio frequency (RF) power source configured to provide an RF bias voltage between the lower electrode and the upper electrode, and a plurality of conductive edge ring segments surrounding the electrostatic chuck and configured for at least one of independent vertical movement relative to the electrostatic chuck or for independently receiving a different RF bias voltage.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: Syo FUKATA, Shoichi MURAKAMI, Shigeru NAKATSUKA, Yusuke OSAWA, Shigehiro FUJINO, Masaaki HIGASHITANI
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Publication number: 20210351058Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.Type: ApplicationFiled: May 6, 2020Publication date: November 11, 2021Inventors: Shoichi MURAKAMI, Shigeru NAKATSUKA, Syo FUKATA, Yusuke OSAWA, Shigehiro FUJINO, Masaaki HIGASHITANI
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DEPOSITION APPARATUS INCLUDING AN OFF-AXIS LIFT-AND-ROTATION UNIT AND METHODS FOR OPERATING THE SAME
Publication number: 20210348272Abstract: A deposition chamber includes a vacuum enclosure, an electrostatic chuck having a flat top surface located within a vacuum enclosure, a lift-and-rotation unit extending through or laterally surrounding the electrostatic chuck at a position that is laterally offset from a vertical axis passing through a geometrical center of the electrostatic chuck, a gas supply manifold configured to provide influx of gas into the vacuum enclosure, and a pumping port connected to the vacuum enclosure.Type: ApplicationFiled: May 7, 2020Publication date: November 11, 2021Inventors: Shoichi MURAKAMI, Shigeru NAKATSUKA, Syo FUKATA, Yusuke OSAWA, Shigehiro FUJINO, Masaaki HIGASHITANI -
Publication number: 20210351059Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.Type: ApplicationFiled: May 6, 2020Publication date: November 11, 2021Inventors: Shoichi MURAKAMI, Shigeru NAKATSUKA, Syo FUKATA, Yusuke OSAWA, Shigehiro FUJINO, Masaaki HIGASHITANI
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Patent number: 10847376Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.Type: GrantFiled: April 10, 2019Date of Patent: November 24, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Yusuke Osawa, Syo Fukata, Naoto Umehara, Sung Tae Lee
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Publication number: 20200006080Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.Type: ApplicationFiled: April 10, 2019Publication date: January 2, 2020Inventors: Yusuke OSAWA, Syo FUKATA, Naoto UMEHARA, Sung Tae LEE
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Patent number: 9978768Abstract: A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.Type: GrantFiled: June 29, 2016Date of Patent: May 22, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jiyin Xu, Ryoichi Honma, Syo Fukata
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Publication number: 20180006041Abstract: A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Jiyin XU, Ryoichi HONMA, Syo FUKATA
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Patent number: 9305935Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.Type: GrantFiled: February 25, 2015Date of Patent: April 5, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
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Publication number: 20150179663Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.Type: ApplicationFiled: February 25, 2015Publication date: June 25, 2015Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
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Patent number: 8994099Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.Type: GrantFiled: August 27, 2014Date of Patent: March 31, 2015Assignee: Sandisk Technologies Inc.Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
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Publication number: 20140367759Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.Type: ApplicationFiled: August 27, 2014Publication date: December 18, 2014Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
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Patent number: 8828884Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.Type: GrantFiled: May 23, 2012Date of Patent: September 9, 2014Assignee: Sandisk Technologies Inc.Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
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Publication number: 20130313627Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Applicant: SanDisk Technologies, Inc.Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata