Patents by Inventor Syoichi Nakagawa

Syoichi Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multilayer circuit board having no local warp on mounting surface thereof
    Patent number: 6217990
    Abstract: A multilayer circuit board for holding a flip chip thereon includes laminated first to fourth substrates. A first pattern integrated portion having a locally high pattern density is provided on the second substrate. Further, on the fourth substrate which is disposed on an opposite side of the second substrate with respect to a center in a laminated direction of the circuit board, a second pattern integrated portion having a locally high pattern density is disposed to correspond to the first pattern integrated portion. Accordingly, a local warp can be prevented from being produced on the mounting surface of the multilayer circuit board when the circuit board is manufactured by baking.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: April 17, 2001
    Assignees: Denso Corporation, Kyocera Corporation
    Inventors: Yasutomi Asai, Takashi Nagasaka, Shinji Ota, Takashi Yamazaki, Shinya Terao, Syoichi Nakagawa