Abstract: A semiconductor memory device including a reset signal generator for generating a reset signal for resetting a bit line pair to an equal potential when a chip selection control signal represents a nonselection state of a memory chip. The reset signal has a reset period longer than a predetermined period even when the period of the chip selection control state representing the nonselection state is shorter than the predetermined period, thereby ensuring resetting the bit line pair and the shortening of accessing time.

Abstract: A semiconductor memory device used, for example, for a video RAM device which stores picture data and which is used in a video display device, etc. The semiconductor memory device includes an internal address generating circuit which sequentially generates row addresses, an address switching circuit which switches between the row address output from the internal address generating circuit and an external address, and a plurality of internal shift registers each of which stores a plurality of bit data which is read out in parallel from a memory cell array in accordance with the internal row address and/or a plurality bit data which is written-in parallel to the memory cell array in accordance with the internal row address. A serial input/output control circuit for controlling the shift registers is also provided. The input/output control circuit controls each of the shift registers so that each of the shift registers effects a shift operation to serially and continuously input or output data.