Patents by Inventor Syoji Ariizumi

Syoji Ariizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a high resistivity layer in direct contact with a polycrystalline silicon layer of high impurity concentration
    Patent number: 4558343
    Abstract: This invention provides a semiconductor device, which has a high impurity concentration diffusion region such as a drain diffusion region and a resistor comprising a polycrystalline silicon layer (which may be a load of a driver MOS transistor), and in which part of the resistor is in direct contact with the high impurity concentration diffusion region. This invention also provides a method of manufacturing a semiconductor device, which comprises the steps of forming a gate electrode and drain and source diffusion regions along the principal surface of a semiconductor substrate, then forming a polycrystalline silicon resistor layer of a comparatively low impurity concentration such that it is in direct contact with a diffusion region, and subsequently causing impurity diffusion from the diffusion region through thermal treatment to obtain ohmic contact between the diffusion region and resistor layer.
    Type: Grant
    Filed: October 26, 1984
    Date of Patent: December 10, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Syoji Ariizumi, Yasushi Fukatsu, Fujio Masuoka
  • Method of manufacturing a semiconductor device
    Patent number: 4475964
    Abstract: This invention provides a semiconductor device, which has a high impurity concentration diffusion region such as a drain diffusion region and a resistor comprising a polycrystalline silicon layer (which may be a load of a driver MOS transistor), and in which part of the resistor is in direct contact with the high impurity concentration diffusion region. This invention also provides a method of manufacturing a semiconductor device, which comprises the steps of forming a gate electrode and drain and source diffusion regions along the principal surface of a semiconductor substrate, then forming a polycrystalline silicon resistor layer of a comparatively low impurity concentration such that it is in direct contact with a diffusion region, and subsequently causing impurity diffusion from the diffusion region through thermal treatment to obtain ohmic contact between the diffusion region and resistor layer.
    Type: Grant
    Filed: October 24, 1983
    Date of Patent: October 9, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Syoji Ariizumi, Yasushi Fukatsu, Fujio Masuoka