Patents by Inventor Syotaro Ono

Syotaro Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818750
    Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 27, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Takafumi Koumoto
  • Publication number: 20200303495
    Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.
    Type: Application
    Filed: August 15, 2019
    Publication date: September 24, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki YAMASHITA, Syotaro ONO, Hisao ICHIJO, Takafumi KOUMOTO
  • Patent number: 10749022
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 18, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro Ono, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10720523
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: July 21, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Hideto Sugawara, Hiroshi Ohta
  • Publication number: 20200119142
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type between the first semiconductor region and the first plane, third semiconductor regions of a first conductivity type provided between the first semiconductor region and the first plane and provided between the second semiconductor regions, a fourth semiconductor region provided between the second semiconductor regions and the first plane, and having a higher second conductivity-type impurity concentration than the second semiconductor regions, a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the first plane, a sixth semiconductor region provided between the second semiconductor regions and the fourth semiconductor region, and having a higher electric resistance per unit depth than the second semiconductor regions, a gate electrode, and a gat
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Syotaro Ono, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10600777
    Abstract: A semiconductor device includes a semiconductor body, first to third electrodes provided on the semiconductor body, and a control electrode. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes first to sixth layers. The second layer of a second conductivity type is selectively provided between the first layer of a first conductivity type and the first electrode. The third layer of the first conductivity type is selectively provided between the second layer and the first electrode. The fourth layer of the second conductivity type is provided between the first layer and the second and third electrodes. The fifth layer of the first conductivity type is selectively provided in the fourth layer and electrically connected to the first electrode. The sixth layer of the first conductivity type is provided in the fourth layer, and electrically connected to the third electrode.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 24, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hisao Ichijo, Syotaro Ono, Hiroaki Yamashita
  • Publication number: 20200091335
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 19, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro ONO, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Publication number: 20200083320
    Abstract: A semiconductor device includes a semiconductor body including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first and second semiconductor layers are alternately arranged in a first direction along a front surface of the semiconductor body, and each include multiple portions arranged in a second direction directed from a back surface toward the front surface of the semiconductor body. The first and second semiconductor layers are configured such that, in an active region, a large/small relationship between amounts of the first conductivity type impurity and the second conductivity type impurity in the portions positioned at the same level in the second direction reverses at a center in the second direction of the second semiconductor layer, and in the terminal region, the large/small relationship reverses alternately in the portions arranged in the second direction.
    Type: Application
    Filed: February 26, 2019
    Publication date: March 12, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroshi Ohta, Syotaro Ono, Hideto Sugawara, Hisao Ichijo, Hiroaki Yamashita
  • Publication number: 20200083215
    Abstract: A semiconductor device includes a semiconductor body, first to third electrodes provided on the semiconductor body, and a control electrode. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes first to sixth layers. The second layer of a second conductivity type is selectively provided between the first layer of a first conductivity type and the first electrode. The third layer of the first conductivity type is selectively provided between the second layer and the first electrode. The fourth layer of the second conductivity type is provided between the first layer and the second and third electrodes. The fifth layer of the first conductivity type is selectively provided in the fourth layer and electrically connected to the first electrode. The sixth layer of the first conductivity type is provided in the fourth layer, and electrically connected to the third electrode.
    Type: Application
    Filed: January 24, 2019
    Publication date: March 12, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hisao Ichijo, Syotaro Ono, Hiroaki Yamashita
  • Publication number: 20200058786
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.
    Type: Application
    Filed: January 7, 2019
    Publication date: February 20, 2020
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Hideto Sugawara, Hiroshi Ohta
  • Patent number: 10411117
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane, a first semiconductor region of a first conductivity type, a second semiconductor region and a third semiconductor region of a second conductivity type, the first semiconductor region interposed between the third semiconductor region and the second semiconductor region, a first well region of a first conductivity type, a second well region of a first conductivity type separated from the first well region, a first contact region of a first conductivity type, a second contact region of a first conductivity type, a gate electrode provided on the first semiconductor region between the first well region and the second well region, a source electrode having a first region in contact with the first contact region and a second region in contact with the second contact region, and a drain electrode.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: September 10, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronics Devices & Storage Corporation
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo
  • Publication number: 20190109215
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane, a first semiconductor region of a first conductivity type, a second semiconductor region and a third semiconductor region of a second conductivity type, the first semiconductor region interposed between the third semiconductor region and the second semiconductor region, a first well region of a first conductivity type, a second well region of a first conductivity type separated from the first well region, a first contact region of a first conductivity type, a second contact region of a first conductivity type, a gate electrode provided on the first semiconductor region between the first well region and the second well region, a source electrode having a first region in contact with the first contact region and a second region in contact with the second contact region, and a drain electrode.
    Type: Application
    Filed: February 22, 2018
    Publication date: April 11, 2019
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo
  • Publication number: 20190088738
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type between the first semiconductor region and the first plane, third semiconductor regions of a first conductivity type provided between the first semiconductor region and the first plane and provided between the second semiconductor regions, a fourth semiconductor region provided between the second semiconductor regions and the first plane, and having a higher second conductivity-type impurity concentration than the second semiconductor regions, a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the first plane, a sixth semiconductor region provided between the second semiconductor regions and the fourth semiconductor region, and having a higher electric resistance per unit depth than the second semiconductor regions, a gate electrode, and a gat
    Type: Application
    Filed: February 22, 2018
    Publication date: March 21, 2019
    Inventors: Syotaro Ono, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10211331
    Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a second conductivity type third semiconductor region, a first conductivity type fourth semiconductor region, a gate insulating portion, a gate electrode, and first and second electrodes. The first semiconductor region includes first and second portions. The second semiconductor region includes third and fourth portions. The gate electrode is on the gate insulating portion and over the first semiconductor region and a portion of the third semiconductor region. The first electrode is on, and electrically connected to, the fourth semiconductor region. The second electrode is over the first portion, the third portion, and the gate electrode, and spaced from the first electrode.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Ichijo, Syotaro Ono, Masahiro Shimura, Hideyuki Ura, Hiroaki Yamashita
  • Publication number: 20180350974
    Abstract: According to one embodiment, the insulating film is provided on a side surface of a second semiconductor layer located at an end in the lateral direction of the second semiconductor layers, or a side surface of a third semiconductor layer located at an end in the lateral direction of the third semiconductor layers. The semiconductive film is provided on a side surface of the insulating film. The semiconductive film is electrically connected to the first electrode and the second electrode. The semiconductive film has a resistivity higher than a resistivity of one of the second semiconductor layers and a resistivity of one of the third semiconductor layers, and lower than a resistivity of the insulating film.
    Type: Application
    Filed: December 4, 2017
    Publication date: December 6, 2018
    Inventors: Hideki Okumura, Syotaro Ono, Naoki Kusunoki, Shingo Sato
  • Patent number: 10103222
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region, a third semiconductor region of the first conductivity type provided on a part of the second semiconductor region, agate electrode, a first electrode, and a conductive portion. The gate electrode is provided on another part of the second semiconductor region via a gate insulating portion. The first electrode is provided on the third semiconductor region and electrically connected to the third semiconductor region. The conductive portion is provided on another part of the first semiconductor region via a first insulating portion and electrically connected to the first electrode, and includes a portion arranged side by side with the gate electrode in a second direction perpendicular to a first direction from the first semiconductor region to the first electrode.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 16, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroaki Katou, Syotaro Ono, Masahiro Shimura, Hideyuki Ura
  • Publication number: 20170263747
    Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a second conductivity type third semiconductor region, a first conductivity type fourth semiconductor region, a gate insulating portion, a gate electrode, and first and second electrodes. The first semiconductor region includes first and second portions. The second semiconductor region includes third and fourth portions. The gate electrode is on the gate insulating portion and over the first semiconductor region and a portion of the third semiconductor region. The first electrode is on, and electrically connected to, the fourth semiconductor region. The second electrode is over the first portion, the third portion, and the gate electrode, and spaced from the first electrode.
    Type: Application
    Filed: August 30, 2016
    Publication date: September 14, 2017
    Inventors: Hisao ICHIJO, Syotaro ONO, Masahiro SHIMURA, Hideyuki URA, Hiroaki YAMASHITA
  • Publication number: 20170207302
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region, a third semiconductor region of the first conductivity type provided on a part of the second semiconductor region, agate electrode, a first electrode, and a conductive portion. The gate electrode is provided on another part of the second semiconductor region via a gate insulating portion. The first electrode is provided on the third semiconductor region and electrically connected to the third semiconductor region. The conductive portion is provided on another part of the first semiconductor region via a first insulating portion and electrically connected to the first electrode, and includes a portion arranged side by side with the gate electrode in a second direction perpendicular to a first direction from the first semiconductor region to the first electrode.
    Type: Application
    Filed: August 30, 2016
    Publication date: July 20, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroaki KATOU, Syotaro ONO, Masahiro SHIMURA, Hideyuki URA
  • Patent number: 9704953
    Abstract: According to one embodiment, a semiconductor device includes a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a gate electrode. An impurity concentration of the second conductivity type of the third semiconductor region is higher than an impurity concentration of the second conductivity type of the second semiconductor regions. The fourth semiconductor region is provided on the first semiconductor regions. The gate electrode provided on the fourth semiconductor region with a gate insulation layer interposed. The gate electrode extends in a third direction. The third direction intersects the first direction. The third direction is parallel to a plane including the first direction and the second direction.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: July 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hideyuki Ura, Masahiro Shimura
  • Patent number: 9590093
    Abstract: In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The third semiconductor region includes a first portion and a second portion. The first portion is provided between the second semiconductor regions adjacent to each other. An amount of impurity of the second conductivity type in the first portion is greater than an amount of impurity of the first conductivity type in the second semiconductor region contiguous to the first portion. The second portion is arranged with a part of the first semiconductor region. An amount of impurity of the second conductivity type in the second portion is smaller than an amount of impurity of the first conductivity type in the part of the first semiconductor region.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: March 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Hideyuki Ura, Masahiro Shimura, Hiroaki Yamashita