Patents by Inventor Syouichi Kotani

Syouichi Kotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8421187
    Abstract: A first insulating film includes five extension lines formed between connection pad portions of adjacent two predetermined wiring lines. The first insulating film also includes peripheral portions of the adjacent two connection pad portions on both sides of the five extension lines. A second insulating film made of a polyimide resin or the like is formed on the upper surface of the first insulating layer by a screen printing method or ink jet method. Since a short circuit may be easily caused by electromigration in a region where the five extension lines are parallel to another, the short circuit due to the electromigration can be prevented by covering only that region with the second insulating film. Accordingly, the region where the second insulating film is formed can be as small as possible, and the semiconductor wafer does not easily warp.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: April 16, 2013
    Assignee: Teramikros, Inc.
    Inventor: Syouichi Kotani
  • Patent number: 7944064
    Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: May 17, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinji Wakisaka, Tomohiro Ito, Shigeru Yokoyama, Osamu Kuwabara, Norihiko Kaneko, Syouichi Kotani
  • Publication number: 20110031584
    Abstract: A first insulating film includes five extension lines formed between connection pad portions of adjacent two predetermined wiring lines. The first insulating film also includes peripheral portions of the adjacent two connection pad portions on both sides of the five extension lines. A second insulating film made of a polyimide resin or the like is formed on the upper surface of the first insulating layer by a screen printing method or ink jet method. Since a short circuit may be easily caused by electromigration in a region where the five extension lines are parallel to another, the short circuit due to the electromigration can be prevented by covering only that region with the second insulating film. Accordingly, the region where the second insulating film is formed can be as small as possible, and the semiconductor wafer does not easily warp.
    Type: Application
    Filed: August 2, 2010
    Publication date: February 10, 2011
    Applicant: Casio Computer Co., Ltd.
    Inventor: Syouichi KOTANI
  • Publication number: 20070164432
    Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 19, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventors: Shinji Wakisaka, Tomohiro Ito, Shigeru Yokoyama, Osamu Kuwabara, Norihiko Kaneko, Syouichi Kotani