Abstract: A channel search device is provided, which includes: a quasi-synchronization quadrature detector for outputting an I-axis signal and a Q-axis signal obtained by performing quasi-synchronization quadrature detection, based on the carrier frequency set value, on a PSK modulation signal; a timing reproducer for reproducing and outputting the I-axis signal and the Q-axis signal while correcting an error of the symbol rate set value; and a dispersion detector for detecting a dispersion between the amplitude of a symbol, comprising the I-axis signal and the Q-axis signal, and a reference amplitude. The channel search device monitors the above-described dispersion while varying the carrier frequency set value and the symbol rate set value, and judges that a channel of the symbol rate set value at the present time exists at the position of the carrier frequency set value when the size of the dispersion detected by the dispersion detector becomes an extremal value.

Abstract: A skew detector calculates symbol amplitudes from a first signal (SI? signal) on an I channel side and a second signal (SQ? signal) on a Q channel side to be inputted into a carrier reproduction circuit. The skew detector outputs differences between the calculated symbol amplitudes and a predetermined reference amplitude as skew signals. A sine-wave generator generates two orthogonal sine waves from the skew signals which are smoothed via a loop filter. A skew correction unit obtains a multiplied result by multiplying one of the two sine waves (first skew correcting coefficient) and the first signal. The skew correction unit obtains a multiplied result by multiplying the other one of the two sine waves (second skew correcting coefficient) and the second signal. The skew correction unit adds these multiplied results and inputs the added result as a new second signal into the carrier reproduction circuit.

Abstract: A demodulating device capable of high-efficiency, high-accuracy phase noise correction control and improved in quality and reliability. A digital signal generating portion synchronously detects a modulated input signal and subjects the signal to A/D conversion to generate digital signals corresponding to phase axes. A timing recovery portion extracts symbol timing of the digital signals to recover timing. A carrier recovery portion sets a gain for a phase difference between the timing-recovered digital signals in accordance with a phase noise correction signal, and rotates symbols in a direction to suppress phase noise in accordance with an oscillation signal generated based on the gain, to recover carrier.

Abstract: A demodulation apparatus that shortens demodulation time and performs efficient high-quality demodulation control. A digital signal generating section generates digital signals corresponding to phase axes from a modulated input signal. A frequency correction value outputting section outputs a frequency correction value. A frequency correcting section gives a frequency offset to digital signals on the basis of a frequency correction value to generate frequency-corrected signals. A timing recovering section performs timing recovery by extracting symbol timing for frequency-corrected signals. A C/N detecting section detecting C/N from a symbol. An optimum frequency correction value determining section treats a frequency correction value corresponding to the maximum C/N value as an optimum frequency correction value.

Abstract: A channel search device is provided, which includes: a quasi-synchronization quadrature detector for outputting an I-axis signal and a Q-axis signal obtained by performing quasi-synchronization quadrature detection, based on the carrier frequency set value, on a PSK modulation signal; a timing reproducer for reproducing and outputting the I-axis signal and the Q-axis signal while correcting an error of the symbol rate set value; and a dispersion detector for detecting a dispersion between the amplitude of a symbol, comprising the I-axis signal and the Q-axis signal, and a reference amplitude. The channel search device monitors the above-described dispersion while varying the carrier frequency set value and the symbol rate set value, and judges that a channel of the symbol rate set value at the present time exists at the position of the carrier frequency set value when the size of the dispersion detected by the dispersion detector becomes an extremal value.

Abstract: A demodulating device capable of high-efficiency, high-accuracy phase noise correction control and improved in quality and reliability. A digital signal generating portion synchronously detects a modulated input signal and subjects the signal to A/D conversion to generate digital signals corresponding to phase axes. A timing recovery portion extracts symbol timing of the digital signals to recover timing. A carrier recovery portion sets a gain for a phase difference between the timing-recovered digital signals in accordance with a phase noise correction signal, and rotates symbols in a direction to suppress phase noise in accordance with an oscillation signal generated based on the gain, to recover carrier.

Abstract: A demodulation apparatus that shortens demodulation time and performs efficient high-quality demodulation control. A digital signal generating section generates digital signals corresponding to phase axes from a modulated input signal. A frequency correction value outputting section outputs a frequency correction value. A frequency correcting section gives a frequency offset to digital signals on the basis of a frequency correction value to generate frequency-corrected signals. A timing recovering section performs timing recovery by extracting symbol timing for frequency-corrected signals. A C/N detecting section detecting C/N from a symbol. An optimum frequency correction value determining section treats a frequency correction value corresponding to the maximum C/N value as an optimum frequency correction value.

Abstract: A circuit for demodulating a signal having a temporal mixture of different modulation schemes applied thereto includes a synchronization-word-detection unit which detects synchronization words included in the signal, and generates first and second position signals, based on the detected synchronization words, indicative of respective predetermined positions in the signal, a first selection unit which selects the first position signals during a first period, and selects the first position signals and the second position signals during a second period, and a carrier-reproduction unit which carries out frequency capturing during the first period by using the first position signals selected by the first selection unit, and carries out phase capturing during the second period by using the first position signals and the second position signals selected by the first selection unit, thereby reproducing a carrier.

Abstract: A semiconductor integrated circuit generating a stabilized oscillation signal based on an input signal includes a plurality of unit circuits connected in series, each of the unit circuits having at least an oscillator, a divider, and a phase comparator which construct at least one part of a phase-locked loop. In the unit circuit, a frequency of an oscillation output signal of a latter one of the unit circuits is higher than that of an oscillation output signal of a former one of the unit circuits.

Abstract: A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that the baseband signal has crossed a transition level, the control value corresponds to a time difference between a sampling point and a transition-level crossing point of the baseband signal. If the determination is that the baseband signal has not crossed the transition level, the control value is 0. The PLL circuit shortens a lockup time and provides stable operation even if the baseband signal involves an offset.

Abstract: A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that the baseband signal has crossed a transition level, the control value corresponds to a time difference between a sampling point and a transition-level crossing point of the baseband signal. If the determination is that the baseband signal has not crossed the transition level, the control value is 0. The PLL circuit shortens a lockup time and provides stable operation even if the baseband signal involves an offset.