Patents by Inventor Syouji Syukuri

Syouji Syukuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8629481
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: January 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Publication number: 20110140185
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 16, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Patent number: 7910960
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Patent number: 7910922
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Publication number: 20100301334
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Application
    Filed: August 11, 2010
    Publication date: December 2, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Publication number: 20090230448
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Application
    Filed: April 30, 2009
    Publication date: September 17, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Patent number: 7550763
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: June 23, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Publication number: 20070241330
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Application
    Filed: June 13, 2007
    Publication date: October 18, 2007
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Patent number: 7247879
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: July 24, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Patent number: 6831294
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: December 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Publication number: 20040232446
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Application
    Filed: June 23, 2004
    Publication date: November 25, 2004
    Applicant: Renesas Technology Corporation
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto