Abstract: A buffer circuit is provided, which suppresses the fluctuation or deviation of the power supply voltage and the ground voltage that are caused by the logic state change of an address signal applied thereto. The buffer circuit comprises (a) a first inverter circuit having the CMOS configuration; (b) a second inverter circuit having the CMOS configuration; and (c) an equalization circuit for equalizing the first output signal of the first inverter circuit and the second output signal of the second inverter circuit. Each of the first and second inverter circuits is activated or inactivated by a control signal. When the first and second inverter circuits are activated, the equalization circuit is set in the high-impedance state, in which the first inverter circuit generates a first output signal at its output terminal and the second inverter circuit generates a second output signal at its output terminal.