Patents by Inventor Syuichi Kobayashi

Syuichi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090124175
    Abstract: There is provided a double-side polishing method for a wafer of sandwiching a wafer held in a carrier between upper and lower turn tables each having a polishing pad attached thereto and simultaneously polishing both surfaces of the wafer while supplying a slurry to a space between the upper and lower turn tables from a plurality of slurry supply holes provided in the upper turn table, wherein a polishing amount at an outer peripheral portion of the wafer to be polished is adjusted and outer peripheral sag of the wafer is suppressed by supplying the slurry in such a manner that an amount of the slurry supplied from the slurry supply holes provided on an outer side relative to the center of rotation of the upper turn table becomes larger than an amount of the slurry supplied from the slurry supply holes provided on an inner side relative to the same at the time of polishing both the surfaces of the wafer.
    Type: Application
    Filed: June 28, 2006
    Publication date: May 14, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Junichi Ueno, Syuichi Kobayashi
  • Patent number: 6975960
    Abstract: A method for evaluating a wafer configuration includes: obtaining plural wafer configuration profiles from a central wafer portion to an edge portion along the entire periphery at a prescribed angular space; providing a first region for calculating a reference line for each profile in the central side of the wafer; calculating the reference line in the first region; providing a second region in the peripheral side of the wafer outside the first region; extrapolating the reference line calculated in the first region to the second region; analyzing a value obtained by subtracting the reference line value in the second region from an actually measured value in the second region; calculating the maximum value among the values as a surface characteristic and the minimum value among the values as a surface characteristic; and, evaluating configuration uniformity in the peripheral portion of the wafer from plural surface characteristics and surface characteristics.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: December 13, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Makoto Kobayashi, Syuichi Kobayashi
  • Publication number: 20040215418
    Abstract: The present invention provides a method for evaluating a configuration of a wafer from a different viewpoint from the conventional SFQR or the like, a wafer with less troubles in an exposure system or the like, and a sorting method for a good quality wafer.
    Type: Application
    Filed: March 5, 2004
    Publication date: October 28, 2004
    Inventors: Makoto Kobayashi, Syuichi Kobayashi