Patents by Inventor Syuichi Ueno

Syuichi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948754
    Abstract: A three-terminal capacitor includes a main body having a cylindrical or substantially cylindrical shape extending in a first direction and including first and second inner electrodes alternately laminated together with dielectric layers interposed therebetween, a pair of first outer electrodes on two end surfaces of the main body in the first direction and electrically connected to the first inner electrodes, and a second outer electrode electrically connected to the second inner electrodes. The main body includes a projecting portion projecting in a direction perpendicular or substantially perpendicular to the first direction at a position between the pair of first outer electrodes. The second outer electrode is provided on one surface of the projecting portion viewable when viewed in the first direction.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: April 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shingo Ito, Koichi Ikeda, Ken Takakura, Satoshi Yoshida, Syuichi Nabekura, Takahiro Hirao, Masanori Nakamura, Kyosuke Uno, Haruhiko Ueno, Yohei Mukobata
  • Publication number: 20090127117
    Abstract: The present invention provides an electrical deionization apparatus suitable for an ultra pure water production system allowing high pressure raw water from an atomic power plant to be reused as the ultra water. The electric deionization stack 10 comprises a plurality of compartments defined by a compartment frame 11 and an ion exchange membrane 12. The compartments at the opposite ends construct an anode compartment 13 and a cathode compartment 14. The compartments, which are located between the anode compartment 13 and the cathode compartment 14, construct at least one concentrating compartment 15 and at least one deionizing compartment 16. Each compartment frame 11a constructing the concentrating compartment 15 has a concentrated water outlet 17. Each compartment frame 11b constructing the deionizing compartment 16 has a treated water outlet 18. In the pressure vessel 20, a concentrated water chamber 24 and a treated water chamber 25 are partitioned by a partition plate 23.
    Type: Application
    Filed: October 9, 2008
    Publication date: May 21, 2009
    Applicant: EBARA CORPORATION
    Inventors: Shinji MIURA, Syuichi Ueno
  • Publication number: 20070217995
    Abstract: A method for producing hydrogen wherein use is made of a high temperature steam electrolysis apparatus having an electrolysis vessel being partitioned into the anode side and the cathode side by the use of a solid oxide electrolyte film as a diaphragm, steam is fed to the above cathode side and a reducing gas is fed to the anode side, and steam electrolysis is carried out at a high temperature, characterized in that the reducing gas and the steam fed to the electrolysis vessel has a temperature of 200 to 500° C.
    Type: Application
    Filed: February 17, 2005
    Publication date: September 20, 2007
    Inventors: Chi Matsumura, Takahiro Oshita, Syuichi Ueno, Hideyuki Misawa, Masahiro Hagiwara, Itaru Shirasawa, Hiroshi Yokota, Akira Uchino, Junichi Hayakawa, Shinichi Isaka
  • Patent number: 6841440
    Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: January 11, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kuroi, Syuichi Ueno, Katsuyuki Horita
  • Publication number: 20030143810
    Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.
    Type: Application
    Filed: January 28, 2003
    Publication date: July 31, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takashi Kuroi, Syuichi Ueno, Katsuyuki Horita
  • Patent number: 6541825
    Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: April 1, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Kuroi, Syuichi Ueno, Katsuyuki Horita
  • Patent number: 6387743
    Abstract: A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: May 14, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuomi Shiozawa, Syuichi Ueno, Yasuyoshi Itoh
  • Publication number: 20020038901
    Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.
    Type: Application
    Filed: March 15, 2001
    Publication date: April 4, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takashi Kuroi, Syuichi Ueno, Katsuyuki Horita
  • Publication number: 20020024095
    Abstract: An object is to obtain a semiconductor device manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls (15a) and (15b) respectively adjacent to boron-containing side walls (10a) and (10b). An interlayer insulating film (48) of silicon nitride etc. is then formed on the silicon nitride film (14).
    Type: Application
    Filed: October 18, 2001
    Publication date: February 28, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuomi Shiozawa, Syuichi Ueno, Yasuyoshi Itoh
  • Patent number: 6333540
    Abstract: A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: December 25, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuomi Shiozawa, Syuichi Ueno, Yasuyoshi Itoh
  • Patent number: 5504307
    Abstract: A heat transfer material for heating and heating unit and heating apparatus using the same material, wherein the heat transfer material comprises a substrate 2 and an electrical insulating layer 4 as a first layer, an electrically conductive layer 5 entirely or partially provided as a second layer, and a heat insulating layer 6 as a third layer, all of which are formed in turn on the substrate 2, whereby a heat transfer material for heating which is capable of insulating a substance to be heated and highly heat efficiency uniformly heating and which has rapid thermal response is obtained.
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: April 2, 1996
    Assignee: Ebara Corporation
    Inventors: Tadamasa Hayashi, Jyunichi Yamaji, Toyoshi Mizushima, Syuichi Ueno, Toshiyuki Koya, Takashi Ohtu, Masashi Fukuhara