Patents by Inventor Syuichi Yamada

Syuichi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a circuit member for a resin-sealed semiconductor device
    Patent number: 6658734
    Abstract: There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: December 9, 2003
    Assignee: Dai Nippon Insatsu Kabushiki Kaisha
    Inventors: Syuichi Yamada, Makoto Nakamura, Takayuki Takeshita, Hiroshi Yagi
  • Resin sealed semiconductor device, circuit member for use therein and method of manufacturing circuit member
    Patent number: 6465734
    Abstract: There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: October 15, 2002
    Assignee: Dai Nippon Insatsu Kabushiki Kaisha
    Inventors: Syuichi Yamada, Makoto Nakamura, Takayuki Takeshita, Hiroshi Yagi
  • Resin sealed semiconductor device, circuit member for use therein
    Patent number: 6359221
    Abstract: There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: March 19, 2002
    Assignee: Dai Nippon Insatsu Kabushiki Kaisha
    Inventors: Syuichi Yamada, Makoto Nakamura, Takayuki Takeshita, Hiroshi Yagi
  • Resin sealed semiconductor device, circuit member for use therein and method of manufacturing circuit member
    Publication number: 20020029894
    Abstract: There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside
    Type: Application
    Filed: November 16, 2001
    Publication date: March 14, 2002
    Applicant: DAI NIPPON INSATSU KABUSHIKI KAISHA
    Inventors: Syuichi Yamada, Makoto Nakamura, Takayuki Takeshita, Hiroshi Yagi
  • Resin sealed semiconductor device, circuit member for use therein and method of manufacturing circuit member
    Publication number: 20010007285
    Abstract: There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside
    Type: Application
    Filed: March 13, 2001
    Publication date: July 12, 2001
    Applicant: Dai Nippon Insatsu Kabushiki Kaisha
    Inventors: Syuichi Yamada, Makoto Nakamura, Takayuki Takeshita, Hiroshi Yagi