Patents by Inventor Syuji Matsuda

Syuji Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7478311
    Abstract: In an error detection method of the present invention, target code strings which are inputted in a discontinuous arrangement are subjected to a syndrome operation, and simultaneously, the target code strings which are inputted in a discontinuous arrangement are subjected to a first error detection code operation while correcting the inter-data continuity by skipping the data so that the arrangement of the code strings have continuity. Then, error data positions and error data numerical values of the target code strings are calculated on the basis of a syndrome obtained in the syndrome operation, and only the error data position among the target code strings are subjected to a second error detection code operation again on the basis of the error data positions and the error data numerical values.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: January 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Syuji Matsuda, Hiroyuki Yabuno
  • Publication number: 20070033506
    Abstract: In an error detection method of the present invention, as shown in FIG. 1, target code strings which are inputted in a discontinuous arrangement are subjected to a syndrome operation, and simultaneously, the target code strings which are inputted in a discontinuous arranged are subjected to a first error detection code operation while correcting the inter-data continuity by skipping the data so that the arrangement of the code strings have continuity. Then, error data positions and error data numerical values of the target code strings are calculated on the basis of a syndrome obtained in the syndrome operation, and only the error data position among the target code strings are subjected to a second error detection code operation again on the basis of the error data positions and the error data numerical values.
    Type: Application
    Filed: August 19, 2004
    Publication date: February 8, 2007
    Inventors: Syuji Matsuda, Hiroyuki Yabuno
  • Publication number: 20050050425
    Abstract: In an error correction method for performing error correction on an error correction unit block in which main data are interleaved, after rearranging code lines in the order of error correction, it is judged whether the corresponding erasure position information indicates “erasure of data” or not with respect to only byte positions in a code line at a boundary between a main data area and a sub data area or a SY area, and erasure position information is set for only positions where erasure position information should be newly obtained. With respect to other byte positions, erasure position information at the same byte positions in a previous code line in the error correction order is set. However, when the previous code line is an error-incorrectable code line, erasure position information is set for all byte positions in a code line that is next to the incorrectable code line in the error correction order.
    Type: Application
    Filed: June 2, 2003
    Publication date: March 3, 2005
    Applicant: Matsushita Electric Industrial Co. Ltd.
    Inventors: Syuji Matsuda, Takashi Nakamura