Abstract: The invention provides a communication control device that includes a self-diagnostic test circuit capable of executing an operation test. The communication control circuit includes a PHY circuit on an LSI with little trouble, and at a operating speed that is equivalent to actual operation. The self-diagnostic test circuit includes: test data creation circuit for creating test data; expected value data creation circuit for creating expected values of the test data after processing; an arbitration signal switching circuit that switches arbitration signals such that test data supplied from the output driver can be received by a receiver of the same twisted-pair drive block as the output driver; and a comparison circuit that compares test data supplied from an output driver and received by a receiver of the same twisted-pair drive block as the output driver with the expected value data and creates match flags.

Abstract: A FIFO memory device for use in data transfer between data processing apparatuses having different data bus widths, has an input circuit 11 with a data bus width of k bits, an output circuit 12 with a data bus width of N×k bits (where N>1) that outputs data within the FIFO memory device, a writing pointer 2 that points to a data writing address of the FIFO memory device, a reading pointer 4 that points to a data reading address of the FIFO memory device, and a valid/invalid indicating circuit 6 that indicates whether or not data output to the output circuit 12 is valid.

Abstract: The invention provides a communication control device that includes a self-diagnostic test circuit capable of executing an operation test. The communication control circuit includes a PHY circuit on an LSI with little trouble, and at a operating speed that is equivalent to actual operation. The self-diagnostic test circuit includes: test data creation circuit for creating test data; expected value data creation circuit for creating expected values of the test data after processing; an arbitration signal switching circuit that switches arbitration signals such that test data supplied from the output driver can be received by a receiver of the same twisted-pair drive block as the output driver; and a comparison circuit that compares test data supplied from an output driver and received by a receiver of the same twisted-pair drive block as the output driver with the expected value data and creates match flags.

Abstract: In a digital phase locked loop, a coarse stepsize variable delay line and a fine stepsize variable delay line are connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits and lower significant bits. The delayed clock pulse is delivered to the input of a clock tree through which the clock pulse propagates and are supplied to various parts of an integrated circuit chip. A phase detector provides a phase comparison between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree. A delay controller counts the reference clock pulse to produce a count value, and increments or decrements the count value in accordance with the output of the phase detector.