Abstract: In an active region and an edge termination region, a drift layer is constituted by a same SJ structure with a parallel pn layer. In the edge termination region, a p+-type extension portion between the active region and a JTE structure fixes the JTE structure to the potential of a source electrode. The p+-type extension portion is between and in contact with a p-type base extension portion and the parallel pn layer. The p+-type extension portion is an extension of upper portions of p+-type regions provided in the active region to mitigate electric field near bottoms of gate trenches. Between the p-type base extension portion and the parallel pn layer is free of the lower portions of the p+-type regions. Thus, a length in the depth direction of the p-type column regions of the edge termination region is longer than that of the p-type column regions of the active region.

Abstract: A semiconductor device including a semiconductor substrate; a first parallel pn layer in which first first-conductivity-type column regions and first second-conductivity-type column regions repeatedly alternate with one another in an active region; a second parallel pn layer in which second first-conductivity-type column regions and second second-conductivity-type column regions repeatedly alternate with one another, in a termination region; a device structure provided between the first main surface of the semiconductor substrate and the first parallel pn layer; a first electrode provided at the first main surface and electrically connected to the device structure; and a second electrode provided at the second main surface of the semiconductor substrate. The plurality of second first-conductivity-type column regions and the plurality of second second-conductivity-type column regions are disposed in concentric shapes surrounding a perimeter of the first parallel pn layer in a plan view.

Abstract: A semiconductor device including a semiconductor substrate, a parallel pn layer and a device structure provided in the semiconductor substrate, first and second electrodes respectively provided at two main surfaces of the semiconductor substrate, the first electrode being electrically connected to the device structure. The parallel pn layer includes first-conductivity-type column regions and second-conductivity-type column regions that are adjacently disposed and repeatedly alternate with one another in a first direction parallel to the first main surface, that each extend in a second direction parallel to the first main surface and orthogonal to the first direction, and that are of a same impurity concentration. A portion of the second-conductivity-type column regions is shorter than the rest thereof. The parallel pn layer has a first portion and a second portion respectively closer to the first and second main surfaces, the first portion being more p-rich, and less n-rich, than the second portion.

Abstract: An insulated gate semiconductor device includes: a carrier transport layer of a first conductivity-type; an injection control region of a second conductivity-type; a carrier supply region of the first conductivity-type; a base contact region of the second conductivity-type; trenches penetrating the injection control region to reach the carrier transport layer; an insulated gate structure provided inside the respective trenches; an upper buried region of the second conductivity-type being in contact with a bottom surface of the injection control region; a lower buried region of the second conductivity-type being in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and a high-concentration region of the first conductivity-type provided inside the carrier transport layer to be in contact with a part of a bottom surface of the lower buried region.

Abstract: An insulated gate semiconductor device includes: a carrier transport layer of a first conductivity-type; an injection control region of a second conductivity-type; a carrier supply region of the first conductivity-type provided at an upper part of the injection control region; a base contact region of the second conductivity-type provided at an upper part of the injection control region; trenches penetrating the injection control region to reach the carrier transport layer; an insulated gate structure provided inside the respective trenches; an upper buried region of the second conductivity-type being in contact with a bottom surface of the injection control region; and a lower buried region of the second conductivity-type being in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches, wherein the lower buried region is separated from each other via the carrier transport layer between the trenches.

Abstract: A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, first base regions of the second conductivity type, second base regions of the second conductivity type, gate insulating films, gate electrodes, a first electrode, a second electrode, and trenches. Between the trenches, the first base regions are in contact with the second semiconductor layer. The second base regions are provided at positions facing the trenches in a depth direction, respectively, and have a first surface facing the second electrode and a second surface facing the first electrode, where a curvature of the first surface is smaller than a curvature of the second surface.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; trenches penetrating the second semiconductor layer and the first semiconductor region, and reaching the first semiconductor layer; gate electrodes on gate insulating films in the trenches; a first base region between the trenches; and second base regions at bottoms of the trenches. The first base region includes a lower region equal in thickness to the second base regions and an upper region on the lower region. The first base region has impurity concentration peaks of local maximum values in a thickness direction. A peak nearest an interface between the upper and lower regions is located at a position furthest from any other peak.

Abstract: Insulated gate semiconductor device includes drift layer of first conductivity type; first base region of second conductivity type on the drift layer; carrier-supply region of the first conductivity type on the first base region and having higher impurity concentration than the drift layer; a first contact region of the second conductivity type on the first base region and having higher impurity concentration than the first base regions; cell-pillars each having polygonal-shape, arranged in a lattice-pattern, sidewalls of the cell-pillars are defined by trenches penetrating the carrier-supply region, the first contact region, and the first base region; and insulated-gate electrode-structures in the trenches. A first pillar selected from the cell-pillars includes the carrier-supply region, the first contact region and the first base region, and the first contact regions are in contact with a limited portion of an outer periphery of a first pillar at a top surface of the first pillar.

Abstract: A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, first base regions of the second conductivity type, second base regions of the second conductivity type, gate insulating films, gate electrodes, a first electrode, a second electrode, and trenches. Between the trenches, the first base regions are in contact with the second semiconductor layer. The second base regions are provided at positions facing the trenches in a depth direction, respectively, and have a first surface facing the second electrode and a second surface facing the first electrode, where a curvature of the first surface is smaller than a curvature of the second surface.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; trenches penetrating the second semiconductor layer and the first semiconductor region, and reaching the first semiconductor layer; gate electrodes on gate insulating films in the trenches; a first base region between the trenches; and second base regions at bottoms of the trenches. The first base region includes a lower region equal in thickness to the second base regions and an upper region on the lower region. The first base region has impurity concentration peaks of local maximum values in a thickness direction. A peak nearest an interface between the upper and lower regions is located at a position furthest from any other peak.

Abstract: Insulated gate semiconductor device includes drift layer of first conductivity type; first base region of second conductivity type on the drift layer; carrier-supply region of the first conductivity type on the first base region and having higher impurity concentration than the drift layer; a first contact region of the second conductivity type on the first base region and having higher impurity concentration than the first base regions; cell-pillars each having polygonal-shape, arranged in a lattice-pattern, sidewalls of the cell-pillars are defined by trenches penetrating the carrier-supply region, the first contact region, and the first base region; and insulated-gate electrode-structures in the trenches. A first pillar selected from the cell-pillars includes the carrier-supply region, the first contact region and the first base region, and the first contact regions are in contact with a limited portion of an outer periphery of a first pillar at a top surface of the first pillar.