Abstract: A Bi-CMOS semiconductor device includes a P-type semiconductor substrate, an N-type buried layer formed in the semiconductor substrate, a P-type well region formed on the buried layer, and an N-channel MOS transistor formed in a first predetermined area of the well region. The Bi-CMOS semiconductor device further includes an N-type surrounding layer formed to surround the well region in cooperation with the buried layer. The surrounding layer electrically isolates the well region from the substrate and the other P-type well region.

Abstract: A semiconductor device comprises a semiconductor chip and a memory array constituted by a plurality of memory blocks formed in the semiconductor chip and each having the essentially same construction and a plurality of bit lines arranged in columns at a predetermined interval. The semiconductor device further comprises a dummy wiring pattern arranged ajacent to the memory array in the semiconductor chip and including a dummy wiring layer set apart from outermost bit lines of each memory block a distance equal to the predetermined interval.

Abstract: A semiconductor integrated cirucit for generating a reference voltage, including a semiconductor substrate, a first voltage terminal connected to a first voltage source, a resistor connected to the first voltage terminal, a second voltage terminal connected to a second voltage source, an intrinsic MOS and having a source, a drain, a gate and a channel having no ion-implantation for threshold control, a first wiring connected to the resistor and the source, a second wiring connected to the second voltage terminal and the drain, a third wiring connected to the drain and the gate, and an output terminal connected to the first wiring for connecting the resistor to the source.

Abstract: A buffer circuit includes first and second differential amplification type buffer circuits. The input nodes of the first and second differential amplification type buffer circuits are connected together and the output nodes of the first and second differential amplification type buffer circuits are also connected to each other. The first differential amplification type buffer circuit is constituted by a pair of driving P-channel MOS transistors and N-channel MOS transistors acting as loads of the P-channel MOS transistors and connected to constitute a current mirror circuit. The second differential amplification type buffer circuit is constituted by P-channel MOS transistors acting as loads and connected to constitute a current mirror circuit and a pair of driving N-channel MOS transistors.

Abstract: First sense amplifiers formed of N-channel transistors are disposed between first and second memory cell blocks. Second sense amplifiers formed of P-channel transistors are disposed between second and third memory cell blocks. Switching transistors are disposed between the sense amplifiers and the memory cell blocks in order to select a particular memory cell block in response to signals applied to the gates thereof.

Abstract: Element regions which are adjacent to each other in a channel width direction are displaced from each other in a channel length direction by 1/4 pitch. Cell plate electrodes are formed over the element regions through a capacitor insulation film to extend in an oblique direction. Groove portions formed in a step-form corresponding to the shape of the respective transistor forming regions of the element regions are each formed between corresponding two adjacent ones of the cell plate electrodes. Word lines are formed in a stripe configuration to extend in a channel width direction and used to directly apply potentials to the element regions. Contact holes are formed for contact hole opening preparation regions of the element regions. Bit lines are formed in a stripe configuration to extend in a length width direction and are connected to respective element regions (1) via the contact holes.

Abstract: First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad.

Abstract: A signal line runs in parallel with first to fourth bit lines on a memory cell array of a dynamic memory device. The signal line runs between and along the first and third bit lines, turns at a predetermined position, turns again and runs between and along the second and fourth bit lines. The predetermined turning position is a position corresponding to the half of the bit line length. The result is that the stray capacitances between the signal line and these bit lines are equal at about 1/2C.sub.F.

Abstract: A semiconductor memory comprises a memory cell for storing data, a bit line pair for transfering the data, a sense amplifier for amplifying the data from the bit line pair, a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory, and a pair of constant voltage barrier transistors connected between the restore circuit and the sense amplifier for increasing the speed of sensing.

Abstract: In a semiconductor integrated circuit, power lines or ground lines of a plurality of circuit blocks having equivalent functions are coupled via a switch circuit to a common main power line or main ground line on a semiconductor integrated circuit chip or semiconductor wafer. The main power line is supplied with power source potential and said main ground line with ground potential. A switch control circuit selectively switches the switch circuit ON or OFF so that defective circuit blocks may be deactivated.

Abstract: Two or more voltage bootstrap circuits are included, and are sequentially operated. A continuous data write/read operation can be performed at a high speed. One of the two voltage bootstrap circuits is used for the data write/read operation and the other thereof is used for the refresh operation, thereby shortening the time required for refreshing.

Abstract: Address signals are decoded by partial decoders, to generate in-phase and complementary signals. These signals are selectively input to main decoders consisting of NAND circuits. Further, these signals are fed via through programming fuse elements to a NOR gate. The fuse elements and the NOR gate form a programmable spare decoder. When the bit selected by the main decoder is defective, the output of this main decoder is shut off. Further, the fuse element of the spare decoder is opened corresponding to the main decoder to select the defective bit, thereby to replace the defective bit with the spare bit.

Abstract: The dynamic memory device of the present invention is formed on an integrated semiconductor substrate subjected to alpha radiation and comprises a switching transistor having a switching terminal, an input-output terminal and a memory terminal; a bit line couple to said input-output terminal for supplying a charge to said transistor; a word line coupled to said switching terminal for controlling the switching of said transistor; and, an R-C circuit coupled to the memory terminal and comprising a charge storage capacitor for storing the charge supplied from said bit line and for substantially preventing loss of the stored charge due to particle radiation.

Abstract: A semiconductor dynamic memory device includes a plurality of memories, row decoders for selecting the row of the memories, column decoders for selecting the column of memories, and sense amplifier circuits connected to the memories, respectively. The dynamic memory device further has a driving circuit for selectively activating some of the sense amplifier circuits in accordance with the content of a predetermined bit of row address data supplied to the row decoders.