Abstract: A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically connected to a first data line. A second terminal of the analog switch is electrically connected to an input terminal of the first inverter, an output terminal of the second inverter, and an input terminal of the clocked inverter. An output terminal of the first inverter is electrically connected to an input terminal of the second inverter. An output terminal of the clocked inverter is electrically connected to a second data line. Each of the analog switch and the clocked inverter is electrically connected to at least one word line. The word line electrically connected to the analog switch is different from the word line electrically connected to the clocked inverter.

Abstract: As operations of an SRAM, there are writing and reading operations, and only a portion of the whole memory operates during performing these operations, while another portion thereof stores a value. By lowering a current consumed in a period of storing this value, a semiconductor device with low power consumption is provided. The present invention provides a semiconductor device with reduced drive voltage in a period of storing a value, compared with a period of writing a value or a period of reading a value. Such a semiconductor device includes a power supply control circuit including an OR circuit electrically connected to a word line, an inverter circuit electrically connected to the OR circuit, and a transistor electrically connected to the OR circuit and the inverter circuit.

Abstract: A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically connected to a first data line. A second terminal of the analog switch is electrically connected to an input terminal of the first inverter, an output terminal of the second inverter, and an input terminal of the clocked inverter. An output terminal of the first inverter is electrically connected to an input terminal of the second inverter. An output terminal of the clocked inverter is electrically connected to a second data line. Each of the analog switch and the clocked inverter is electrically connected to at least one word line. The word line electrically connected to the analog switch is different from the word line electrically connected to the clocked inverter.

Abstract: As operations of an SRAM, there are writing and reading operations, and only a portion of the whole memory operates during performing these operations, while another portion thereof stores a value. By lowering a current consumed in a period of storing this value, a semiconductor device with low power consumption is provided. The present invention provides a semiconductor device with reduced drive voltage in a period of storing a value, compared with a period of writing a value or a period of reading a value. Such a semiconductor device includes a power supply control circuit including an OR circuit electrically connected to a word line, an inverter circuit electrically connected to the OR circuit, and a transistor electrically connected to the OR circuit and the inverter circuit.