Patents by Inventor Syuuichi Osaka

Syuuichi Osaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050176173
    Abstract: A chip-on-board module has a multilayer interconnection board having die mount sections; dies mounted on respective die mount sections such that a single die is mounted on each die mount section or two or more dies are being stacked and mounted there; bonding pads provided on the multilayer and connected to single dies or uppermost dies; contact pads provided on the multilayer board and connected to corresponding bonding pads; jumper pads provided in proximity to the contact pads and connected to edge terminals of the multilayer board, circuit elements mounted on the multilayer interconnection board, or through holes formed so as to extend across layers of the multilayer board; and molding resin for molding the dies and the pads. The uppermost dies of the respective die mount sections where dies are stacked in two or more layers have passed an electric property test.
    Type: Application
    Filed: April 11, 2005
    Publication date: August 11, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Naoyuki Shinonaga, Hideyuki Akagi, Syuuichi Osaka
  • Publication number: 20030020155
    Abstract: A chip-on-board module has a multilayer interconnection board having die mount sections; dies mounted on respective die mount sections such that a single die is mounted on each die mount section or two or more dies are being stacked and mounted there; bonding pads provided on the multilayer and connected to single dies or uppermost dies; contact pads provided on the multilayer board and connected to corresponding bonding pads; jumper pads provided in proximity to the contact pads and connected to edge terminals of the multilayer board, circuit elements mounted on the multilayer interconnection board, or through holes formed so as to extend across layers of the multilayer board; and molding resin for molding the dies and the pads. The uppermost dies of the respective die mount sections where dies are stacked in two or more layers have passed an electric property test.
    Type: Application
    Filed: September 24, 2002
    Publication date: January 30, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoyuki Shinonaga, Hideyuki Akagi, Syuuichi Osaka
  • Publication number: 20020025608
    Abstract: Testing of memory chips is facilitated. Further, memory chips which have failed a test can be readily replaced with new non-defective memory chips. Efforts and costs required for replacing defective memory chips with non-defective memory chips can be reduced. A memory module has a circuit board having mounted thereon a plurality of bonding pad groups, a plurality of contact pad groups, a plurality of jumper pad groups, and a plurality of through hole groups, which are assigned to respective chip mount areas. According to a method of manufacturing a memory chip, memory chips are tested through use of the contact pad groups before being encapsulated with molding resin, and there is used a test connector having POGO pins which are brought into contact with corresponding contact pad groups.
    Type: Application
    Filed: March 6, 2001
    Publication date: February 28, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoyuki Shinonaga, Hideyuki Akagi, Syuuichi Osaka