Abstract: A semiconductor integrated circuit reliability verification device for detecting any portion of design that may cause circuit malfunction due to the effects of switching noise, comprises a partial circuit network detecting part for detecting, based on a transistor-level net list for the circuit to be verified, information concerning partial circuit networks that form part of a circuit to be verified, a maximum resistance calculating part for calculating, based on the information concerning the partial circuit network, the maximum resistance that occurs while the channel connected component is operating, a gate capacitance calculating part for calculating, based on the information concerning the partial circuit network, the total gate capacitance for the portions but the inverter of a driven circuit, and an error judging part for calculating the value of evaluation function, based on the value of maximum resistance and the total gate capacitance, and judging whether or not the calculated value is in violation

Abstract: In order to verify a design of an integrated circuit in terms of a peak current density limit of electromigration specifications, a plurality of transistors, included in a given net of the integrated circuit, are assorted into a plurality of transistor groups. This assortment is based on different logical states which the given net is capable of assuming. Following this, both a lead resistance and load capacitance of the net are determined. Further, a plurality of peak currents respectively associated with the transistor groups are determined using the lead resistance and the load capacitance. Subsequently, a check is made to determine a maximum peak current among the plurality of peak currents already obtained. A peak current density of the maximum peak currents is determined using data of lead shapes, after which a check is further made to determine if the peak current density exceeds the peak current density limit of electromigration specifications.