Abstract: A structure of an image sensor for sensing the light of an image impinging thereupon and for translating the image into a standard television format is disclosed. The structure comprises a plurality of first and second light detecting elements (22, 23) arranged in rows and columns and half as many rows and columns as scan lines of a television format for generating respective analog signals in proportion to the intensity of the light impinging respectively on each of the first and second light detecting elements (22, 23), wherein the first and second light detecting elements in each row are alternately disposed and activated by first read lines RDOn (n=1 . . . 256) to generate odd field signals, and wherein the first and second light detecting elements (22, 23) of two adjacent rows disposed in a zigzag or serrated manner are activated by second read lines RDEn (n=1 . . . 256) to generate even field signals.

Abstract: In a CMOS-type image sensor, a plurality of pairs of light-detecting elements (LDEs) are arranged in rows and columns to generate analog signals proportional to the intensity of light impinging on respective one of the LDEs. First and second photo sensing means in each pair of LDEs are coupled in parallel, in the column direction, at a floating sensing point through first turn-on means. The first and second photo sensing means in adjacent pairs of LDEs are coupled in parallel in the column direction through second turn-on means. The first turn-on means are enabled by first control lines and the second turn-on means are enabled by second control lines coupled thereto, respectively. Analog signals acquired in the first and second photo sensing means of one pair or of adjacent pairs are present at the floating sensing point in response to the enabling of the first or second control lines, respectively.

Abstract: A method for initializing a counter within a corresponding set of A/D converters of N sets of A/D converters of a single-chip CMOS-type image sensor in order to minimize none uniformity across the N sets of A/D converters is provided. The single chip CMOS type image sensor includes an image sense array having N columns of output lines for outputting N analog signals respectively; and a signal process device for generating N sets of digital signal each of which corresponds to one of N analog signals respectively. The signal process device has N input lines and N sets of A/D converter each of which including a counter for generating one of the N sets of digital signal respectively. The method comprises the steps of applying a predetermined reference voltage at each of N input lines of the signal process device such that a compensation value corresponding to each set of A/D converter is obtained.

Abstract: A method of making accurate alignment layers in a liquid crystal display (LCD) cell is provided so that the LCD seal band can be placed as close to the pixel as possible. This method is implemented by ablating the apolyimide film on the glass substrates of the LCD cell to remove the alignment film where the sealing material is to be dispersed later. Thus, the sealing band can butt against the liquid crystal mixture without any clearance. In so doing, the display area is increased, and the reliability of the seal is improved.

Abstract: A liquid crystal display device having a sealing material close to display area while maintaining a uniform liquid crystal cell gap is disclosed. The liquid crystal display comprises two transparent electrode substrates having a trench near the display area to stop the sealing material overflowing to display pixels. Thus, the effective display area of a liquid crystal display device is increased by dispensing a sealing material to a trench area at a predetermined position surrounding the display area. A spacer used in the sealing material is larger in size than that used in the display area to compensate the depth of the trench. After the liquid crystal is injected into the space surrounded by the substrates and a sealing material, a uniform liquid crystal cell gap over the entire display area is obtained.

Abstract: The display area of a liquid crystal display cell is increased by placing conductive epoxy within the boundary which seals the liquid crystal to connect the top glass plate with the bottom glass plate, in contrast with the conventional method of making the electrical connection outside the display area. The conductive epoxy is dispensed in areas not occupied by the liquid crystal patterns. The conductive epoxy can be in the form of particles of spheres or rods serving as spacers for maintaining the gap dimension between the two glass plates. The conductive epoxy can also be integrated with the boundary sealing epoxy or fill a notch cut in the boundary sealing epoxy.

Abstract: The number of external column driver chip can be reduced to one in an active matrix liquid crystal display with column input multiplexing driving scheme. At least two sample and hold circuits are used for each column with alternate sampling and holding periods. Video signals are sampled and held at least twice during one line scanning time. These sample and hold circuits are all integrated in the driver chip.

Abstract: A row select driver circuit is used to energize each pixel row sequentially of a liquid crystal display. The output of each row select driver circuit is connected to a corresponding pixel row line and to a succeeding row select driver circuit as an activating input. All the row select circuits are integrated with thin-film transistors and deposited on the same glass substrate as the pixels. The number of leads connected to the assembly is much less than the number of pixel rows, including six overlapping clock signals (three each for odd-numbered rows and even-numbered rows), a shift-in signal, a positive power supply terminal and at least one ground. In one example, the number of leads is reduced from 240 to 10.

Abstract: A redundant row select driver circuit system is provided for enhancing manufacturing yield and reducing manufacturing costs in the liquid crystal data displays. In particular, a row select driver circuit is provided with redundant subcircuits that can effectively replace any damaged subcircuit within the row select driver circuit. In addition, there is disclosed a capacitance compensating scheme to adjust the gray scale level in a damaged row select line with a break inside the display area. And finally, an enhanced diagnostic scheme is disclosed for testing of each row select driver subcircuits in a active matrix display having row select driver circuits connected to each end of row select lines.

Abstract: An LCD display having at least one redundant data driving circuit on a substrate that can be substituted for a defective data driving circuit on the substrate. These redundant subcircuits are exact copies of a column driving subcircuit except that some of the connecting points to the control and driving signal lines are not hardwired. That is, the connecting points are left as potential welding points. If a column driving circuit that is coupled to a particular input data line is damaged, then a redundant data driving subcircuit can be hardwired by welding the corresponding crossing points to compensate the damaged circuit. The damaged circuit is also disconnected (by using a laser cut or compatible methods) from the corresponding input data line and the internal data line as necessary.

Abstract: Separate circuit sections of active driver circuits located adjacent at least one side of a liquid crystal display have a first encapsulating material covering each of the active driver circuits separately and a second encapsulating material covering all of the active driver circuits and their first encapsulating layer. The active driver circuits may also be sealed between two spaced bands forming an enclosure between the substrates and having an opening in the outer seal to allow a fluid to be inserted in the enclosure formed by the two seal bands to protect the active driver circuits therein. The opening may be sealed with an adhesive.

Abstract: A row select driver circuit is used to energize each pixel row sequentially of a liquid crystal display. The output of each row select driver circuit is connected to a corresponding pixel row line and to a succeeding row select driver circuit as an activating input. All the row select driver circuits are integrated with thin-film transistors and deposited on the same glass substrate as the pixels. The number of leads connected to the assembly is much less than the number of pixel rows, including two sets of overlapping clock signals (three each for odd-numbered rows and even-numbered rows offset by one scanning line time) with different pulsewidths and periods twice as long as the scanning line time, a clock signal with a period as long as the scanning line time, a shift-in signal, a positive power supply terminal and at least one ground.

Abstract: A data driver circuit and system driving scheme that can be integrated directly onto an LCD display substrate to reduce the cost of the peripheral integrated circuits and the hybrid assembly needed by unscanned active matrix liquid crystal displays to connect them to the array. A demultiplexer circuit is deposited on the display for demultiplexing a group of Y columns of multiplexed video data input signals to X groups of Y pixel capacitors that are also deposited on the substrate in Z rows. In addition, a data driver circuit provides voltage signals to precharge the pixel capacitors to a first voltage level in a first time period such that video data input signals coupled thereto in a multiplexed fashion during a second time period causes the pixel capacitors to store to a second predetermined voltage level to provide a video display as the rows of pixels are sequentially scanned.

Abstract: A data driver circuit and system driving scheme that can be integrated directly onto an LCD display substrate to eliminate the cost of the peripheral integrated circuits and the hybrid assembly needed by unscanned active matrix liquid crystal displays to connect them to the array. A demultiplexer circuit is deposited on the display for demultiplexing a group of Y columns of multiplexed video data input signals to X groups of Y pixel capacitors that are also deposited on the substrate in Z rows. In addition, a precharging circuit is deposited on the substrate to precharge the pixel capacitors to a first voltage level such that the video data input signals coupled thereto in a demultiplexed fashion causes the pixels to discharge to a second predetermined voltage level to provide a video display as the rows of pixels are sequentially scanned.

Abstract: A circuit for use with an LCD display wherein the LCD display contains a first number of pixel columns and a second number of pixel rows on a substrate is provided. The circuit comprises a plurality of row select driver circuits corresponding to the number of pixel rows for electrically energizing the pixel rows. The row select driver circuit is deposited on the LCD display substrate and an output of each of the row select driver circuits is electrically connected to a corresponding pixel row and to a successive row select driver circuit as an activating input. Switching apparatus external to the LCD display and having leads electrically connected to the row select driver circuits is also provided for electrically switching the row select driver circuits such that each pixel row is sequentially energized. A corresponding method is also disclosed.

Abstract: A level shifter circuit has a pair of voltage buses, first and second p-channel MOS transistors and third and fourth n-channel MOS transistors. Each transistor has a gate to control conduction. The first and third transistors are connected in series between the voltage buses and the second and fourth transistors are connected in series between the voltage buses. A node between the first and second transistors is connected to the gates of the second and fourth transistors. An input signal having one of first and second levels is applied to the gate of the first transistor while the inverse of the input signal is applied to the gate of the second transistor. One voltage bus is connected through one of the second and fourth transistors in response to the first level input signal. The other voltage bus is connected the other of the second and fourth transistors in response to the second level input signal.