Patents by Inventor Sze-An Wu

Sze-An Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6759347
    Abstract: A method of reducing plasma induced damage in semiconductor devices and fluorine damage to a metal containing layer including providing a semiconductor wafer including semiconductor devices including a gate oxide and a process surface including metal lines; carrying out a first high density plasma chemical vapor deposition (HDP-CVD) process to controllably produce a silicon rich oxide (SRO) layer including a relatively increased thickness at a center portion of the process surface compared to a peripheral portion of the process surface; and, carrying out a second HDP-CVD process in-situ to deposit a fluorine doped silicon dioxide layer over the SRO layer to fill a space between the metal lines.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: July 6, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Lung Cheng, Ming-Hwa Yoo, Sze-An Wu, Ying Lung Wang
  • Patent number: 6703317
    Abstract: A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: March 9, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Lung Cheng, Ming-Hwa Yoo, Sze-An Wu, Ying-Lung Wang