Patents by Inventor Sze Ping Goh

Sze Ping Goh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of forming double-sided fan-out wafer level package
    Patent number: 11127668
    Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 21, 2021
    Inventors: Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh, Jose A. Caparas
  • Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package
    Publication number: 20200006215
    Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh, Jose A. Caparas
  • Semiconductor device and method of forming double-sided fan-out wafer level package
    Patent number: 10453785
    Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: October 22, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh, Jose A. Caparas
  • Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package
    Publication number: 20160043047
    Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 11, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh, Jose A. Caparas