Patents by Inventor Szu-chun TSAO
Szu-chun TSAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143008Abstract: A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track IO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Szu-Chun Tsao, Yi-Wen Chen, Jaw-Juinn Horng
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Publication number: 20240086708Abstract: One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Juinn Horng, Szu-Chun Tsao
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Publication number: 20240085934Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.Type: ApplicationFiled: August 18, 2023Publication date: March 14, 2024Inventors: Po-Yu LAI, Szu-Chun TSAO, Jaw-Juinn HORNG
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Patent number: 11906997Abstract: A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track TO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.Type: GrantFiled: November 30, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Szu-Chun Tsao, Yi-Wen Chen, Jaw-Juinn Horng
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Patent number: 11853880Abstract: One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.Type: GrantFiled: August 25, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Jaw-Juinn Horng, Szu-Chun Tsao
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Publication number: 20230377661Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell or ii) a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230350442Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.Type: ApplicationFiled: June 20, 2023Publication date: November 2, 2023Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
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Patent number: 11763891Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell and ii a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.Type: GrantFiled: March 9, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Chun Tsao, Jaw-Juinn Horng
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Patent number: 11733724Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.Type: GrantFiled: August 20, 2021Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Lai, Szu-Chun Tsao, Jaw-Juinn Horng
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Patent number: 11726510Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.Type: GrantFiled: August 27, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230244258Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.Type: ApplicationFiled: April 6, 2023Publication date: August 3, 2023Inventors: Szu-Chun Tsao, Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen
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Patent number: 11669115Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.Type: GrantFiled: August 27, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Chun Tsao, Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen
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Publication number: 20230063492Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Szu-Chun Tsao, Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen
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Publication number: 20230064967Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230053710Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Inventors: Po-Yu Lai, Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230023317Abstract: Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints.Type: ApplicationFiled: March 8, 2022Publication date: January 26, 2023Inventors: Shenggao Li, Szu-Chun Tsao, Wen-Shen Chou
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Publication number: 20220366948Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Juinn Horng, Chin-Ho Chang, Yung-Chow Peng, Szu-Chun Tsao
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Publication number: 20220365550Abstract: A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track TO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.Type: ApplicationFiled: November 30, 2021Publication date: November 17, 2022Inventors: Szu-Chun Tsao, Yi-Wen Chen, Jaw-Juinn Horng
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Patent number: 11430491Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.Type: GrantFiled: February 25, 2021Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Juinn Horng, Chin-Ho Chang, Yung-Chow Peng, Szu-Chun Tsao
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Publication number: 20220231014Abstract: A semiconductor device and a method for a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a core transistor having a drain configured to receive a first voltage, and a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor. Wherein a gate and a source of the first dummy transistor are connected to each other. Wherein a drain of the second dummy transistor is connected to the source of the first dummy transistor. Wherein a gate of the second dummy transistor is connected to the drain of the core transistor.Type: ApplicationFiled: April 20, 2021Publication date: July 21, 2022Inventors: SZU-CHUN TSAO, JAW-JUINN HORNG