Abstract: This invention discloses a memory control module and its associated control method. The memory control module includes a storage unit, an ECC unit, and a read/write control unit. The storage unit is to store a target data. The ECC unit includes multiple first encoders and a second encoder. The first encoders perform an encoding operation on the target data and generate multiple first sets of parity check bits, which comprise at least two lengths. The second encoder performs an encoding operation on the target data and the multiple first sets of parity check bits and generates a second set of parity check bits. The read/write control module converts the target data, the first sets of party check bit sets and the second set of parity check bits into a data format of a memory module.

Abstract: This invention discloses a memory control module and its associated control method. The memory control module includes a storage unit, an ECC unit, and a read/write control unit. The storage unit is to store a target data. The ECC unit includes multiple first encoders and a second encoder. The first encoders perform an encoding operation on the target data and generate multiple first sets of parity check bits, which comprise at least two lengths. The second encoder performs an encoding operation on the target data and the multiple first sets of parity check bits and generates a second set of parity check bits. The read/write control module converts the target data, the first sets of party check bit sets and the second set of parity check bits into a data format of a memory module.

Abstract: An apparatus for random parity check and correction with BCH code is provided, including a Bose-Chaudhuri-Hocquenghem (BCH) parity check code encoder, a channel, a BCH parity check code decoder, and a static random access memory (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in writing to flash memory. The channel is connected to the BCH parity check code encoder to compute the parity check code and the message polynomial into receiving data. The BCH parity check code decoder is connected to the channel for inputting the receiving data and using BCH decoding to compute the eigen value and error address. The SRAM is connected to the BCH parity check code decoder so as to read error address from static RAM, correct the data and restores the corrected data to the SRAM. Therefore, this achieves the object of random parity check and correction with BCH code.

Abstract: An apparatus for random parity check and correction with BCH code is provided, including a BCH parity check code encoder, a channel, a BCH parity check code decoder, and a static RAM (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in writing to flash memory. The channel is connected to the BCH parity check code encoder to compute the parity check code and the message polynomial into receiving data. The BCH parity check code decoder is connected to the channel for inputting the receiving data and using BCH decoding to compute the eigen value and error address. The SRAM is connected to the BCH parity check code decoder so as to read error address from static RAM, correct the data and restores the corrected data to the SRAM. Therefore, this achieves the object of random parity check and correction with BCH code.

Abstract: An Optical Sub-Assembly housing structure for an optical transceiver module includes a plastic housing holding the light source unit on the inside, the housing having a tubular front coupling portion adapted to hold an optical fiber cable, the tubular front coupling portion having a tapered front opening for guiding the inserted optical fiber cable into position, and a longitudinal slot that makes the tubular front coupling portion deformable for high precision positioning and re-connection performance of the inserted optical fiber cable.