Patents by Inventor Szu-Hao LAI
Szu-Hao LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9825039Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor body, a first doped region, a second doped region, a gate and a dielectric layer. The semiconductor body is disposed on a dielectric substrate and has a protrusion portion, a first portion and a second portion. The first portion and the second portion are respectively disposed at two opposite sides of the protrusion portion. The first doped region is disposed in a top of the protrusion portion. The second doped region is disposed in an end of the first portion far away from the protrusion portion. The gate is disposed on the first portion and adjacent to the protrusion portion. The dielectric layer is disposed between the gate and the protrusion portion, and between the gate and the first portion.Type: GrantFiled: October 18, 2016Date of Patent: November 21, 2017Assignee: United Microelectronics Corp.Inventors: Po-Hsieh Lin, Yi-Chuen Eng, Szu-Hao Lai, Ming-Chih Chen
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Patent number: 9263579Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.Type: GrantFiled: May 27, 2015Date of Patent: February 16, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
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Publication number: 20150263170Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.Type: ApplicationFiled: May 27, 2015Publication date: September 17, 2015Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
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Patent number: 9076652Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.Type: GrantFiled: May 27, 2013Date of Patent: July 7, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
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Patent number: 9034705Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.Type: GrantFiled: March 26, 2013Date of Patent: May 19, 2015Assignee: United Microelectronics Corp.Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
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Patent number: 9012324Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.Type: GrantFiled: August 24, 2012Date of Patent: April 21, 2015Assignee: United Microelectronics Corp.Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
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Patent number: 9000568Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.Type: GrantFiled: September 26, 2011Date of Patent: April 7, 2015Assignee: United Microelectronics Corp.Inventors: Szu-Hao Lai, Yu-Ren Wang, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Te-Lin Sun
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Publication number: 20140349467Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.Type: ApplicationFiled: May 27, 2013Publication date: November 27, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
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Patent number: 8853060Abstract: An epitaxial process includes the following step. A recess is formed in a substrate. A seeding layer is formed to cover a surface of the recess. A buffer layer is formed on the seeding layer. An etching process is performed on the buffer layer to homogenize and shape the buffer layer. An epitaxial layer is formed on the homogenized flat bottom shape buffer layer.Type: GrantFiled: May 27, 2013Date of Patent: October 7, 2014Assignee: United Microelectronics Corp.Inventors: Szu-Hao Lai, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Ming-Hua Chang, Yu-Shu Lin, Tsai-Yu Wen, Hsin-Kuo Hsu
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Publication number: 20140295629Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.Type: ApplicationFiled: March 26, 2013Publication date: October 2, 2014Applicant: United Microelectronics Corp.Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
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Publication number: 20140057434Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
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Patent number: 8551876Abstract: A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.Type: GrantFiled: August 18, 2011Date of Patent: October 8, 2013Assignee: United Microelectronics Corp.Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh
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Publication number: 20130075874Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.Type: ApplicationFiled: September 26, 2011Publication date: March 28, 2013Inventors: Szu-Hao Lai, Yu-Ren Wang, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Te-Lin Sun
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Publication number: 20130045594Abstract: A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh
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Publication number: 20130012012Abstract: A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer.Type: ApplicationFiled: July 10, 2011Publication date: January 10, 2013Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen, Shao-Wei Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh
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Publication number: 20120306028Abstract: A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided.Type: ApplicationFiled: May 30, 2011Publication date: December 6, 2012Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Chien-Liang Lin, Shao-Wei Wang, Ying-Wei Yen
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Publication number: 20120071004Abstract: A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jei-Ming CHEN, Szu-Hao LAI