Patents by Inventor Szu-Hsien Liu
Szu-Hsien Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10937891Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.Type: GrantFiled: July 30, 2018Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Fu-Jier Fan, Kong-Beng Thei, Szu-Hsien Liu
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Patent number: 10916542Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: GrantFiled: March 4, 2016Date of Patent: February 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
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Patent number: 10868141Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.Type: GrantFiled: July 1, 2016Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Fu-Jier Fan, Kong-Beng Thei, Szu-Hsien Liu
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Publication number: 20200083343Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Patent number: 10516029Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: GrantFiled: June 11, 2019Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Publication number: 20190296121Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Patent number: 10340357Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: GrantFiled: April 27, 2018Date of Patent: July 2, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Publication number: 20190097013Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: ApplicationFiled: April 27, 2018Publication date: March 28, 2019Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Publication number: 20180350801Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: ApplicationFiled: July 25, 2018Publication date: December 6, 2018Inventors: Yi-huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
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Publication number: 20180337249Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Fu-Jier FAN, Kong-Beng THEI, Szu-Hsien LIU
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Patent number: 9853149Abstract: The present disclosure relates an integrated circuit (IC) and a method for manufacturing same. A polysilicon layer is formed over a first region of a substrate and has a plurality of polysilicon structures that are packed with respect to one another to define a first packing density. A dummy layer is formed over a second region of the substrate and has a plurality of dummy structures that are packed with respect to one another to define a second packing density, where the first packing density and second packing density are substantially similar. An inter-layer dielectric layer is formed over the first region and second region of the substrate. Dishing of at least the second region of the substrate concurrent with a chemical-mechanical polish is generally inhibited by the first packing density and second packing density after forming the inter-layer dielectric layer.Type: GrantFiled: October 3, 2016Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsuing Chen, Fu-Jier Fan, Yi-Huan Chen, Kong-Beng Thei, Ker-Hsiao Huo, Szu-Hsien Liu
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Publication number: 20170194455Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.Type: ApplicationFiled: July 1, 2016Publication date: July 6, 2017Inventors: FU-JIER FAN, KONG-BENG THEI, SZU-HSIEN LIU
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Publication number: 20170194320Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: ApplicationFiled: March 4, 2016Publication date: July 6, 2017Inventors: Yi-huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
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Publication number: 20110026286Abstract: A transformer with power factor compensation and a DC/AC inverter constructed thereby are presented. The power factor compensation transformer includes a primary winding, a secondary winding, and a power factor compensation capacitor bank, while the secondary winding having a coupling winding and a power factor compensation winding. The primary winding connects to a power grid in parallel, the coupling winding connects to an AC output port of a passive trigger type DC/AC inverter, and the power factor compensation winding serially connects with the power factor compensation capacitor bank. Besides, a triggered switch serially connecting with the power factor compensation winding and power factor compensation capacitor bank is provided when an inductor with air gap links the passive trigger type DC/AC inverter and the coupling winding. Consequently, a function of power factor correction is achieved.Type: ApplicationFiled: December 17, 2009Publication date: February 3, 2011Inventors: Wun-Chih LIU, Szu-Hsien LIU, Szu-Lin LIU
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Publication number: 20070032006Abstract: A fabrication method of a flash memory is provided. The substrate having a cell region and a peripheral circuitry region is provided. A patterned dielectric layer and a patterned conductive layer are formed on the substrate, and isolation structures are formed in the substrate. An inter gate dielectric layer and a poly layer are formed sequentially over the substrate. The poly layer and the inter gate dielectric in peripheral circuitry region are removed. After forming a second conductive layer and a mask layer over substrate, memory cells are formed in the cell region and a gate structure is formed in the peripheral circuitry region. A conductive plug is formed above the gate structure for electrically connecting the second conductive layer. Since the inter gate dielectric layer in the peripheral circuitry region is removed, the fabrication of the conductive plug can be simpler and the process window thereof can be improved.Type: ApplicationFiled: January 11, 2006Publication date: February 8, 2007Inventors: Szu-Hsien Liu, Houng-Chi Wei