Abstract: An electronic device is provided, the device comprising an interposer including a dielectric material and an interconnect structure. An integrated circuit chip may be arranged over the interposer. A galvanic capacitor may be spaced from the integrated circuit chip. The galvanic capacitor having a first electrode and a second electrode. The first electrode of the galvanic capacitor may be coupled to the integrated circuit chip. A molding material may be arranged over the integrated circuit chip and the galvanic capacitor, whereby the integrated circuit chip may be spaced from the galvanic capacitor by at least a portion of the molding material.

Abstract: A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.

Abstract: A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.

Abstract: The present disclosure relates to testing structures and, more particularly, to a circuit and method for design of RF integrated circuits for process control monitoring. The circuit includes a radio frequency integrated circuit comprising a plurality of active NFET devices and passive devices arranged in a single topography; and a plurality of NFET switches which are configurable to diagnose physical failures of the plurality of active NFET devices and the passive devices by isolating selected ones of the plurality of active NFET devices and the passive devices into different built-in circuit topologies by selectively turning on and off the plurality of active NFET devices and the passive devices.

Abstract: The present disclosure relates to testing structures and, more particularly, to a circuit and method for design of RF integrated circuits for process control monitoring. The circuit includes a radio frequency integrated circuit comprising a plurality of active NFET devices and passive devices arranged in a single topography; and a plurality of NFET switches which are configurable to diagnose physical failures of the plurality of active NFET devices and the passive devices by isolating selected ones of the plurality of active NFET devices and the passive devices into different built-in circuit topologies by selectively turning on and off the plurality of active NFET devices and the passive devices.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: A test system for testing devices is disclosed. The test system includes a scanning microscope module and a test module. The scanning microscope module, when testing a device under test (DUT), is configured to perturb the DUT with a laser at a test (pixel) location. The test module includes a tester unit, a reference failure log containing prior failing compare vectors of interest, and a comparator unit which includes a software comparator. The tester unit is configured to perform a test run at the test location of the DUT with a test pattern. If the test run fails testing, the tester unit is configured to compare using the comparator unit to determine if failing test vectors of the test run matches a desired failure signature, and to generate a comparator trigger pulse if failing test vectors match the prior failure signature. The trigger pulse indicates that the test location of the DUT is a failed location.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: A test system and method for testing integrated circuits with improved defect localization is disclosed. A laser is used to perturb a device under test (DUT) at a test location. A tester tests the DUT with a test pattern and compares test results with compare vectors in a prior failure log. When a failure signature is matched, a failure signal is generated, indicating that the test location is a failed location. Comparing the test results with the compare vectors in the prior failure log and generating the failure signal when the failure signature is detected reduces artifacts from testing, shortening debug turnaround time.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: A test system for testing devices is disclosed. The test system includes a scanning microscope module and a test module. The scanning microscope module, when testing a device under test (DUT), is configured to perturb the DUT with a laser at a test (pixel) location. The test module includes a tester unit, a reference failure log containing prior failing compare vectors of interest, and a comparator unit which includes a software comparator. The tester unit is configured to perform a test run at the test location of the DUT with a test pattern. If the test run fails testing, the tester unit is configured to compare using the comparator unit to determine if failing test vectors of the test run matches a desired failure signature, and to generate a comparator trigger pulse if failing test vectors match the prior failure signature. The trigger pulse indicates that the test location of the DUT is a failed location.

Abstract: A test system and method for testing integrated circuits with improved defect localization is disclosed. A laser is used to perturb a device under test (DUT) at a test location. A tester tests the DUT with a test pattern and compares test results with compare vectors in a prior failure log. When a failure signature is matched, a failure signal is generated, indicating that the test location is a failed location. Comparing the test results with the compare vectors in the prior failure log and generating the failure signal when the failure signature is detected reduces artifacts from testing, shortening debug turnaround time.