Patents by Inventor Szu-Hung Chen
Szu-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961779Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: GrantFiled: May 27, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC).Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 11515307Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.Type: GrantFiled: June 4, 2020Date of Patent: November 29, 2022Assignees: National Applied Research Laboratories, EPISTAR CorporationInventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
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Patent number: 10868128Abstract: Semiconductor contact structures, a semiconductor device including the semiconductor contact structures, and a method for forming the same are disclosed. In an embodiment, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer contacting the channel layer; and a contact metal layer over the interface layer, the contact metal layer including aluminum silicon copper alloy (AlSiCu).Type: GrantFiled: February 1, 2019Date of Patent: December 15, 2020Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Jen-Inn Chyi, Cheng-Han Tsou, Szu-Hung Chen
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Publication number: 20200303377Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.Type: ApplicationFiled: June 4, 2020Publication date: September 24, 2020Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
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Patent number: 10727231Abstract: A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.Type: GrantFiled: October 12, 2018Date of Patent: July 28, 2020Assignees: National Applied Research Laboratories, EPISTAR CorporationInventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
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Publication number: 20200006511Abstract: Semiconductor contact structures, a semiconductor device including the semiconductor contact structures, and a method for forming the same are disclosed. In an embodiment, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer contacting the channel layer; and a contact metal layer over the interface layer, the contact metal layer including aluminum silicon copper alloy (AlSiCu).Type: ApplicationFiled: February 1, 2019Publication date: January 2, 2020Inventors: Jen-Inn Chyi, Cheng-Han Tsou, Szu-Hung Chen
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Publication number: 20190043862Abstract: A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.Type: ApplicationFiled: October 12, 2018Publication date: February 7, 2019Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
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Patent number: 10134735Abstract: A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a first fin formed on the Ge-containing film; and a NMOSFET transistor having a second fin formed on the Ge-containing film; wherein the PMOSFET transistor and the NMOSFET transistor compose a CMOS transistor, and the first fin comprises Ge-containing material and the second fin comprises a Group III-V compound.Type: GrantFiled: June 26, 2017Date of Patent: November 20, 2018Assignees: National Applied Research Laboratories, EPISTAR CorporationInventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
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Publication number: 20170373064Abstract: A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a first fin formed on the Ge-containing film; and a NMOSFET transistor having a second fin formed on the Ge-containing film; wherein the PMOSFET transistor and the NMOSFET transistor compose a CMOS transistor, and the first fin comprises Ge-containing material and the second fin comprises a Group III-V compound.Type: ApplicationFiled: June 26, 2017Publication date: December 28, 2017Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
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Patent number: 9281305Abstract: A transistor device structure includes a substrate, a first transistor layer and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure is disposed on the second transistor layer and has a protruding portion. The first transistor unit includes a gate structure, a source/drain structure, an embedded source/drain structure and a channel. The source/drain structure is disposed beside the gate structure and over the insulating structure. The embedded source/drain structure is disposed underneath the source/drain structure and in the insulating structure. The channel is defined between the protruding portion and the gate structure.Type: GrantFiled: December 5, 2014Date of Patent: March 8, 2016Assignee: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Chih-Chao Yang, Jia-Min Shieh, Wen-Hsien Huang, Tung-Ying Hsieh, Chang-Hong Shen, Szu-Hung Chen
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Patent number: 8603882Abstract: A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.Type: GrantFiled: May 13, 2011Date of Patent: December 10, 2013Assignee: National Applied Research LaboratoriesInventors: Szu-Hung Chen, Hung-Min Chen, Yu-Sheng Lai, Wen-Fa Wu, Fu-Liang Yang
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Publication number: 20130320408Abstract: A semiconductor device comprises a substrate, a metal-semiconductor compound layer and at least one kind of metal dopant. The substrate has a surface. The metal-semiconductor compound layer extends downwards into the substrate from the surface. The metal dopant which is made by one of a group of metal elements with atomic numbers ranging from 57 to 78 or the arbitrary combinations thereof and doped in the metal-semiconductor compound layer and the substrate with at least one peak concentration formed adjacent to the interface of the metal-semiconductor compound layer and the substrate.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Inventors: Szu-Hung CHEN, Hung-Min Chen, Wen-Fa Wu
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Patent number: 8535198Abstract: A zero backlash planetary gear train, comprising: a shell, a planetary gear set, and at least a sun gear set. Planetary gear set is disposed in said shell, and includes a planetary arm rack having output axis, such that planetary arm rack in said shell is provided with a plurality of double-layer planetary gears. The planetary gear set includes a first planetary gear and a second planetary gear. A buffer mechanism is provided between first planetary gear and second planetary gear. Said first planetary gear is engaged with at least an internal gear on an inner rim of shell, and second planetary gear is engaged with at least a sun gear set. Sun gear set is provided with a sun gear connected to a driving motor. Said zero backlash planetary gear train is capable of eliminating backlash between gears.Type: GrantFiled: August 13, 2012Date of Patent: September 17, 2013Assignee: National Chung Cheng UniversityInventors: Zhang-Hua Fong, Szu-Hung Chen
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Publication number: 20130199323Abstract: A zero backlash gear structure, comprising: an engaging element, a compound gear set, an elastic element, and a fixing element. Wherein, the engaging element is provided with a plurality of engaging slots. The compound gear set includes a compound gear, a gear shaft, and a spline; wherein, the compound gear is provided with at least two gears, said plurality of gears can be engaged to a plurality of engaging slots. Said fixing element is sleeved onto said gear shaft, to press against said plurality of gears and said elastic element. When backlash occurs, said elastic element is used to make said plurality of gears on said compound gear set to get close to each other automatically, so that said fixing element and said compound gear set can move in synchronism, thus achieving zero backlash in both forward and reverse rotations.Type: ApplicationFiled: August 13, 2012Publication date: August 8, 2013Inventors: Zhang-Hua Fong, Szu-Hung Chen
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Publication number: 20130203553Abstract: A zero backlash planetary gear train, comprising: a shell, a planetary gear set, and at least a sun gear set. Planetary gear set is disposed in said shell, and includes a planetary arm rack having output axis, such that planetary arm rack in said shell is provided with a plurality of double-layer planetary gears. The planetary gear set includes a first planetary gear and a second planetary gear. A buffer mechanism is provided between first planetary gear and second planetary gear. Said first planetary gear is engaged with at least an internal gear on an inner rim of shell, and second planetary gear is engaged with at least a sun gear set. Sun gear set is provided with a sun gear connected to a driving motor. Said zero backlash planetary gear train is capable of eliminating backlash between gears.Type: ApplicationFiled: August 13, 2012Publication date: August 8, 2013Inventors: Zhang-Hua FONG, Szu-Hung Chen
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Publication number: 20120190163Abstract: A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.Type: ApplicationFiled: May 13, 2011Publication date: July 26, 2012Applicant: National Applied Research LaboratoriesInventors: Szu-Hung Chen, Hung-Min Chen, Yu-Sheng Lai, Wen-Fa Wu, Fu-Liang Yang
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Patent number: 7501348Abstract: A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the ?-shaped metal gate with nano scale line-width can be formed.Type: GrantFiled: April 10, 2007Date of Patent: March 10, 2009Assignee: National Chiao Tung UniversityInventors: Szu-Hung Chen, Yi-Chung Lien, Yi Edward Chang
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Publication number: 20080254632Abstract: A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the ?-shaped metal gate with nano scale line-width can be formed.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Applicant: National Chiao Tung UniversityInventors: Szu-Hung Chen, Yi-Chung Lien, Edward Yi Chang
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Publication number: 20070066051Abstract: A method for forming a gate pattern for an electronic device, comprising steps of: providing a substrate, whereon a first photo-resist layer is formed; performing a first photo-lithography process so as to form a first pattern with a first width on the substrate; forming a second photo-resist layer, covering the first pattern and the first photo-resist layer on the substrate; and performing a second photo-lithography process, which is shifted from the first photo-lithography process, so as to form a second pattern with a second width on the substrate; wherein the second width is smaller than the first width.Type: ApplicationFiled: December 2, 2005Publication date: March 22, 2007Inventors: Szu-Hung Chen, Chien-I Kuo, Edward Chang