Patents by Inventor SZU-JU HUANG
SZU-JU HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071849Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
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Publication number: 20230385521Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Yi-Lin CHUANG, Shih-Yao LIN, Szu-ju HUANG, Yin-An CHEN, Shih Feng HONG
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Publication number: 20230385520Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Yi-Lin CHUANG, Shih-Yao LIN, Szu-ju HUANG, Yin-An CHEN, Shih Feng HONG
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Patent number: 11816417Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: GrantFiled: February 22, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Henry Lin, Szu-ju Huang, Yin-An Chen, Amos Hong
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Publication number: 20230214575Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Yi-Lin Chuang, Szu-ju Huang, Shih-Yao Lin, Shih Feng Hong, Yin-An Chen
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Patent number: 11604917Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: GrantFiled: August 9, 2021Date of Patent: March 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Patent number: 11263375Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.Type: GrantFiled: June 30, 2020Date of Patent: March 1, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Szu-Ju Huang, Shih-Feng Hong
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Publication number: 20210365620Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.Type: ApplicationFiled: June 30, 2020Publication date: November 25, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Szu-Ju HUANG, Shih-Feng HONG
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Publication number: 20210365624Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Patent number: 11087066Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: GrantFiled: September 21, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Publication number: 20210174000Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Inventors: Yi-Lin Chuang, Henry Lin, Szu-ju Huang, Yin-An Chen, Amos Hong
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Patent number: 10943049Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: GrantFiled: May 1, 2019Date of Patent: March 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Publication number: 20210004519Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Patent number: 10810346Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: GrantFiled: June 3, 2019Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Publication number: 20200104457Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.Type: ApplicationFiled: May 1, 2019Publication date: April 2, 2020Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Publication number: 20200104458Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.Type: ApplicationFiled: June 3, 2019Publication date: April 2, 2020Inventors: Yi-Lin Chuang, Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong
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Patent number: 10268795Abstract: A method for timing optimization is disclosed. The method includes obtaining information on detour locations of a chip by performing a routing operation, establishing, through machine learning, a model that describes a relationship between an image map and the detour locations, generating predicted detour locations based on the model and the image map, determining the probability of detouring in a region of the predicted detour locations, determining a predicted detour net for a path in a region having a high probability of detour, and determining sensitivity of the path.Type: GrantFiled: April 20, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Yi-Lin Chuang, Chih-Tien Chang, Kuan-Hua Su, Szu-Ju Huang
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Publication number: 20180307790Abstract: A method for timing optimization is disclosed. The method includes obtaining information on detour locations of a chip by performing a routing operation, establishing, through machine learning, a model that describes a relationship between an image map and the detour locations, generating predicted detour locations based on the model and the image map, determining the probability of detouring in a region of the predicted detour locations, determining a predicted detour net for a path in a region having a high probability of detour, and determining sensitivity of the path.Type: ApplicationFiled: April 20, 2017Publication date: October 25, 2018Inventors: YI-LIN CHUANG, CHIH-TIEN CHANG, KUAN-HUA SU, SZU-JU HUANG
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Patent number: D1024051Type: GrantFiled: August 10, 2021Date of Patent: April 23, 2024Assignee: Acer IncorporatedInventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng