Abstract: A calibration device includes a comparison unit, a counting unit, a memory, and a compensation circuit. A residue of a sub analog-to-digital converter is compared with a first and a second voltage by the comparison unit for generating a comparison result. A number of times of the residue voltage, out of bounds defined by the first and the second voltage, is counted by the counting unit in an ith period according to the comparison result. The number of times of the residue voltage out of the bounds in an (i?1)th period is stored in the memory. A clock of the sub ADC is adjusted by the compensation circuit into a direction based on the number of times of the residue voltage out of the bounds in the ith period and the number of times of the residue voltage out of the bounds in the (i?1)th period.

Abstract: A calibration device comprises a comparison unit, a counting unit, a memory, and a compensation circuit. A residue of a sub analog-to-digital converter is compared with a first and a second voltage by the comparison unit for generating a comparison result. A number of times of the residue voltage, out of bounds defined by the first and the second voltage, is counted by the counting unit in an ith period according to the comparison result. The number of times of the residue voltage out of the bounds in an (i?1)th period is stored in the memory. A clock of the sub ADC is adjusted by the compensation circuit into a direction based on the number of times of the residue voltage out of the bounds in the ith period and the number of times of the residue voltage out of the bounds in the (i?1)th period.

Abstract: A common centroid symmetric structure capacitor is provided, which includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer is adjacent to the second metal layer, the third metal layer is adjacent to the first metal layer, the fourth metal layer is adjacent to the second metal layer, and the first metal layer is symmetric to the fourth metal layer, the second metal layer is symmetric to the third metal layer. Each of the metal layers has two sets of metal wires, each set has a plurality of metal wires, and each of the metal wires in each set is arranged in an interlaced manner.

Abstract: An analog-to-digital converter with calibration is provided. The converter includes at least one conversion unit. The conversion unit includes a comparator, a control unit, a count unit, and a calibration unit. The comparator compares the voltage of the first input terminal with the voltage of the second input terminal and outputs a comparison result. The control unit outputs a control signal according to a comparison result of the comparator and a selecting signal. The count unit performs a count operation according to the control signal and outputs a count result. The calibration unit provides a reference voltage to the second input terminal of the comparator, and adjusts the level of the reference voltage according to the count result of the count unit. Thus, reference voltage is included inside each conversion unit and conventional resistor ladder producing reference voltage can be removed.

Abstract: A face-centered cubic structure capacitor is provided, which includes a first metal layer, a second metal layer, and a connection layer. The first metal layer comprises a plurality of first metal wires, a plurality of second metal wires, and a plurality of first metal blocks. The first and second metal wires are intercrossed with each other to form a grid structure, and each of the first metal blocks is disposed in each grid of the grid structure. The second metal layer comprises a plurality of third metal wires, a plurality of fourth metal wires, and a plurality of second metal blocks. The third and fourth metal wires are intercrossed with each other to form a grid structure, and each of the second metal blocks is disposed in each grid of the grid structure. The connection layer comprises a plurality of third metal blocks and a plurality of fourth metal blocks.

Abstract: A comparator is provided. In a first period, input terminal of the pre-amplifier is coupled to a first voltage. A first terminal of the first capacitor is coupled to the second input terminal of the pre-amplifier. A second terminal of the first capacitor is coupled to the first input voltage in the first period, and is coupled to the second input voltage in the second period. The second capacitor is coupled between the output terminal of the pre-amplifier and an input terminal of the gain unit. The switch is coupled between the input terminal and an output terminal of the gain unit. An input terminal of the latch is coupled to the output terminal of the gain unit. The latch outputs a comparison result.

Abstract: A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.

Abstract: The comparison device includes a first through second comparators, a chop switching unit, a delta-sigma modulation unit, and a first through second compensation units. The chop switching unit transmits a first and a second signals to two input terminals of the first comparator during a first period, and inverses the first and second signals during a second period. The delta-sigma modulation unit compares the comparison results of two parallel comparators and generates the digital control codes for the comparators with the awareness of the chop switching unit. The first and the second compensation units adjust the threshold voltages of the comparators according to the digital control codes and a step size for calibrating the offset voltages of two comparators. The calibration scheme requiring no assumption on the input signal statistics is background thus the comparison device will not interrupt normal operation and is immune to PVT variations.

Abstract: An analog-to-digital converter with calibration is provided. The converter includes at least one conversion unit. The conversion unit includes a comparator, a control unit, a count unit, and a calibration unit. The comparator compares the voltage of the first input terminal with the voltage of the second input terminal and outputs a comparison result. The control unit outputs a control signal according to a comparison result of the comparator and a selecting signal. The count unit performs a count operation according to the control signal and outputs a count result. The calibration unit provides a reference voltage to the second input terminal of the comparator, and adjusts the level of the reference voltage according to the count result of the count unit. Thus, reference voltage is included inside each conversion unit and conventional resistor ladder producing reference voltage can be removed.

Abstract: A face-centered cubic structure capacitor is provided, which includes a first metal layer, a second metal layer, and a connection layer. The first metal layer comprises a plurality of first metal wires, a plurality of second metal wires, and a plurality of first metal blocks. The first and second metal wires are intercrossed with each other to form a grid structure, and each of the first metal blocks is disposed in each grid of the grid structure. The second metal layer comprises a plurality of third metal wires, a plurality of fourth metal wires, and a plurality of second metal blocks. The third and fourth metal wires are intercrossed with each other to form a grid structure, and each of the second metal blocks is disposed in each grid of the grid structure. The connection layer comprises a plurality of third metal blocks and a plurality of fourth metal blocks.

Abstract: A common centroid symmetric structure capacitor is provided, which includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer is adjacent to the second metal layer, the third metal layer is adjacent to the first metal layer, the fourth metal layer is adjacent to the second metal layer, and the first metal layer is symmetric to the fourth metal layer, the second metal layer is symmetric to the third metal layer. Each of the metal layers has two sets of metal wires, each set has a plurality of metal wires, and each of the metal wires in each set is arranged in an interlaced manner.

Abstract: A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.

Abstract: A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.