Patents by Inventor Szu-Ping Wang
Szu-Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11600709Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.Type: GrantFiled: June 30, 2022Date of Patent: March 7, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
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Publication number: 20220336606Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
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Publication number: 20220271137Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.Type: ApplicationFiled: March 31, 2021Publication date: August 25, 2022Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
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Patent number: 11417742Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.Type: GrantFiled: March 31, 2021Date of Patent: August 16, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
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Patent number: 11374109Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.Type: GrantFiled: October 31, 2019Date of Patent: June 28, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
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Patent number: 11362186Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.Type: GrantFiled: March 27, 2020Date of Patent: June 14, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Lung Li, Chih-Hao Pan, Szu-Ping Wang, Po-Hsuan Chen, Chi-Cheng Huang
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Publication number: 20210265474Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.Type: ApplicationFiled: March 27, 2020Publication date: August 26, 2021Applicant: United Microelectronics Corp.Inventors: Kuo-Lung Li, Chih-Hao Pan, Szu-Ping Wang, Po-Hsuan Chen, Chi-Cheng Huang
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Publication number: 20210134979Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Applicant: United Microelectronics Corp.Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng